GPIO_NXP_Arduino 0.1.1
GPIO device operation sample code for Arduino
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GPIO_NXP.h
1
8#ifndef ARDUINO_GPIO_NXP_ARD_H
9#define ARDUINO_GPIO_NXP_ARD_H
10
11#include <Arduino.h>
12#include <stdint.h>
13
14#include <I2C_device.h>
15
21enum access_word : uint8_t
22{
23 IN,
24 OUT,
25 POLARITY,
26 CONFIG,
27 DRIVE_STRENGTH,
28 LATCH,
29 PULL_UD_EN,
30 PULL_UD_SEL,
31 INT_MASK,
32 INT_STATUS,
33 OUTPUT_PORT_CONFIG,
34 NUM_access_word,
35};
36
44class GPIO_base : public I2C_device
45{
46public:
47
49 enum board {
50 NONE,
51 ARDUINO_SHIELD,
52 };
53
55 const int n_bits;
56
58 const int n_ports;
59
67 GPIO_base( uint8_t i2c_address, const int nbits, const uint8_t* arp, uint8_t ai );
68
70 virtual ~GPIO_base();
71
82 void begin( board env = NONE );
83
92 void output( int port, uint8_t value, uint8_t mask = 0 );
93
100 void output( uint8_t *vp );
101
109 uint8_t input( int port );
110
118 uint8_t* input( uint8_t *vp );
119
128 void config( int port, uint8_t config, uint8_t mask = 0 );
129
136 void config( uint8_t* vp );
137
145 void write_port( access_word w, uint8_t* vp );
146
154 void write_port16( access_word w, uint16_t* vp );
155
164 uint8_t* read_port( access_word w, uint8_t* vp );
165
174 uint16_t* read_port16( access_word w, uint16_t* vp );
175
184 void write_port( access_word w, uint8_t value, int port_num = 0 );
185
194 void write_port16( access_word w, uint16_t value, int port_num = 0 );
195
204 uint8_t read_port( access_word w, int port_num = 0 );
205
214 uint16_t read_port16( access_word w, int port_num = 0 );
215
216 static void print_bin( uint8_t v );
217
218private:
219 const uint8_t* arp;
220 const uint8_t auto_increment;
221 bool endian;
222
223 static constexpr int RESET_PIN = 8;
224 static constexpr int ADDR_PIN = 9;
225};
226
235{
236public:
237 PCAL6xxx_base( uint8_t i2c_address, const int nbits, const uint8_t arp[], uint8_t ai );
238 virtual ~PCAL6xxx_base();
239};
240
241
247{
248public:
250 enum reg_num {
251 Input_Port,
252 Output_Port,
253 Polarity_Inversion,
254 Configuration,
255 Output_drive_strength_0 = 0x40,
256 Output_drive_strength_1,
257 Input_latch,
258 Pull_up_pull_down_enable,
259 Pull_up_pull_down_selection,
260 Interrupt_mask,
261 Interrupt_status,
262 Output_port_configuration,
263 };
264
265 PCAL6408A( uint8_t i2c_address = (0x40 >> 1) + 0 );
266 virtual ~PCAL6408A();
267
268 static constexpr uint8_t access_ref[ NUM_access_word ] = {
269 Input_Port, // IN,
270 Output_Port, // OUT
271 Polarity_Inversion, // POLARITY
272 Configuration, // CONFIG
273 Output_drive_strength_0, // DRIVE_STRENGTH
274 Input_latch, // LATCHLATCH
275 Pull_up_pull_down_enable, // PULL_UD_EN
276 Pull_up_pull_down_selection, // PULL_UD_SEL
277 Interrupt_mask, // INT_MASK
278 Interrupt_status, // INT_STATUS
279 Output_port_configuration, // OUTPUT_PORT_CONFIG
280 };
281};
282
288{
289public:
291 enum reg_num {
292 Input_Port_0, Input_Port_1,
293 Output_Port_0, Output_Port_1,
294 Polarity_Inversion_port_0, Polarity_Inversion_port_1,
295 Configuration_port_0, Configuration_port_1,
296 Output_drive_strength_register_0=0x40, Output_drive_strength_register_0B,
297 Output_drive_strength_register_1, Output_drive_strength_register_1B,
298 Input_latch_register_0, Input_latch_register_1,
299 Pull_up_pull_down_enable_register_0, Pull_up_pull_down_enable_register_1,
300 Pull_up_pull_down_selection_register_0, Pull_up_pull_down_selection_register_1,
301 Interrupt_mask_register_0, Interrupt_mask_register_1,
302 Interrupt_status_register_0, Interrupt_status_register_1,
303 Output_port_configuration_register,
304 };
305
306 PCAL6416A( uint8_t i2c_address = (0x40 >> 1) + 0 );
307 virtual ~PCAL6416A();
308
309 static constexpr uint8_t access_ref[ NUM_access_word ] = {
310 Input_Port_0, // IN,
311 Output_Port_0, // OUT
312 Polarity_Inversion_port_0, // POLARITY
313 Configuration_port_0, // CONFIG
314 Output_drive_strength_register_0, // DRIVE_STRENGTH
315 Input_latch_register_0, // LATCHLATCH
316 Pull_up_pull_down_enable_register_0, // PULL_UD_EN
317 Pull_up_pull_down_selection_register_0, // PULL_UD_SEL
318 Interrupt_mask_register_0, // INT_MASK
319 Interrupt_status_register_0, // INT_STATUS
320 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
321 };
322};
323
329{
330public:
332 enum reg_num {
333 Input_Port_0, Input_Port_1, Input_Port_2, reserved0,
334 Output_Port_0, Output_Port_1, Output_Port_2, reserved1,
335 Polarity_Inversion_port_0, Polarity_Inversion_port_1, Polarity_Inversion_port_2, reserved2,
336 Configuration_port_0, Configuration_port_1, Configuration_port_2,
337 Output_drive_strength_register_port_0A=0x40, Output_drive_strength_register_port_0B,
338 Output_drive_strength_register_port_1A, Output_drive_strength_register_port_1B,
339 Output_drive_strength_register_port_2A, Output_drive_strength_register_port_2B,
340 reserved3, reserved4,
341 Input_latch_register_port_0, Input_latch_register_port_1, Input_latch_register_port_2, reserved5,
342 Pull_up_pull_down_enable_register_port_0, Pull_up_pull_down_enable_register_port_1, Pull_up_pull_down_enable_register_port_2, reserved6,
343 Pull_up_pull_down_selection_register_port_0, Pull_up_pull_down_selection_register_port_1, Pull_up_pull_down_selection_register_port_2, reserved7,
344 Interrupt_mask_register_port_0, Interrupt_mask_register_port_1, Interrupt_mask_register_port_2, reserved8,
345 Interrupt_status_register_port_0, Interrupt_status_register_port_1, Interrupt_status_register_port_2, reserved9,
346 Output_port_configuration_register, reserved10, reserved11, reserved12,
347 Interrupt_edge_register_port_0A, Interrupt_edge_register_port_0B,
348 Interrupt_edge_register_port_1A, Interrupt_edge_register_port_1B,
349 Interrupt_edge_register_port_2A, Interrupt_edge_register_port_2B,
350 reserved13, reserved14,
351 Interrupt_clear_register_port_0, Interrupt_clear_register_port_1, Interrupt_clear_register_port_2, reserved15,
352 Input_status_port_0, Input_status_port_1, Input_status_port_2, reserved16,
353 Individual_pin_output_port_0_configuration_register, Individual_pin_output_port_1_configuration_register, Individual_pin_output_port_2_configuration_register, reserved17,
354 Switch_debounce_enable_0, Switch_debounce_enable_1, Switch_debounce_count,
355 };
356
357 PCAL6524( uint8_t i2c_address = (0x44 >> 1) + 0 );
358 virtual ~PCAL6524();
359
360 static constexpr uint8_t access_ref[ NUM_access_word ] = {
361 Input_Port_0, // IN,
362 Output_Port_0, // OUT
363 Polarity_Inversion_port_0, // POLARITY
364 Configuration_port_0, // CONFIG
365 Output_drive_strength_register_port_0A, // DRIVE_STRENGTH
366 Input_latch_register_port_0, // LATCHLATCH
367 Pull_up_pull_down_enable_register_port_0, // PULL_UD_EN
368 Pull_up_pull_down_selection_register_port_0, // PULL_UD_SEL
369 Interrupt_mask_register_port_0, // INT_MASK
370 Interrupt_status_register_port_0, // INT_STATUS
371 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
372 };
373};
374
380{
381public:
383 enum reg_num {
384 Input_Port_0, Input_Port_1, Input_Port_2, Input_Port_3, Input_Port_4,
385 Output_Port_0, Output_Port_1, Output_Port_2, Output_Port_3, Output_Port_4,
386 Polarity_Inversion_port_0, Polarity_Inversion_port_1, Polarity_Inversion_port_2, Polarity_Inversion_port_3, Polarity_Inversion_port_4,
387 Configuration_port_0, Configuration_port_1, Configuration_port_2, Configuration_port_3, Configuration_port_4,
388 Output_drive_strength_register_port_0A = 0x30, Output_drive_strength_register_port_0B,
389 Output_drive_strength_register_port_1A, Output_drive_strength_register_port_1B,
390 Output_drive_strength_register_port_2A, Output_drive_strength_register_port_2B,
391 Output_drive_strength_register_port_3A, Output_drive_strength_register_port_3B,
392 Output_drive_strength_register_port_4A, reserved0,
393 Input_latch_register_port_0, Input_latch_register_port_1, Input_latch_register_port_2, Input_latch_register_port_3, Input_latch_register_port_4,
394 Pull_up_pull_down_enable_register_port_0, Pull_up_pull_down_enable_register_port_1, Pull_up_pull_down_enable_register_port_2, Pull_up_pull_down_enable_register_port_3, Pull_up_pull_down_enable_register_port_4,
395 Pull_up_pull_down_selection_register_port_0, Pull_up_pull_down_selection_register_port_1, Pull_up_pull_down_selection_register_port_2, Pull_up_pull_down_selection_register_port_3, Pull_up_pull_down_selection_register_port_4,
396 Interrupt_mask_register_port_0, Interrupt_mask_register_port_1, Interrupt_mask_register_port_2, Interrupt_mask_register_port_3, Interrupt_mask_register_port_4,
397 Interrupt_status_register_port_0, Interrupt_status_register_port_1, Interrupt_status_register_port_2, Interrupt_status_register_port_3, Interrupt_status_register_port_4,
398 Output_port_configuration_register,
399 Interrupt_edge_register_port_0A, Interrupt_edge_register_port_0B,
400 Interrupt_edge_register_port_1A, Interrupt_edge_register_port_1B,
401 Interrupt_edge_register_port_2A, Interrupt_edge_register_port_2B,
402 Interrupt_edge_register_port_3A, Interrupt_edge_register_port_3B,
403 Interrupt_edge_register_port_4A, reserved1,
404 Interrupt_clear_register_port_0, Interrupt_clear_register_port_1, Interrupt_clear_register_port_2, Interrupt_clear_register_port_3, Interrupt_clear_register_port_4,
405 Input_status_port_0, Input_status_port_1, Input_status_port_2, Input_status_port_3, Input_status_port_4,
406 Individual_pin_output_port_0_configuration_register, Individual_pin_output_port_1_configuration_register, Individual_pin_output_port_2_configuration_register, Individual_pin_output_port_3_configuration_register, Individual_pin_output_port_4_configuration_register,
407 Switch_debounce_enable_0, Switch_debounce_enable_1,
408 Switch_debounce_count,
409 };
410
411 PCAL6534( uint8_t i2c_address = (0x44 >> 1) + 0 );
412 virtual ~PCAL6534();
413
414 static constexpr uint8_t access_ref[ NUM_access_word ] = {
415 Input_Port_0, // IN,
416 Output_Port_0, // OUT
417 Polarity_Inversion_port_0, // POLARITY
418 Configuration_port_0, // CONFIG
419 Output_drive_strength_register_port_0A, // DRIVE_STRENGTH
420 Input_latch_register_port_0, // LATCHLATCH
421 Pull_up_pull_down_enable_register_port_0, // PULL_UD_EN
422 Pull_up_pull_down_selection_register_port_0, // PULL_UD_SEL
423 Interrupt_mask_register_port_0, // INT_MASK
424 Interrupt_status_register_port_0, // INT_STATUS
425 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
426 };
427};
428
429#endif // ARDUINO_GPIO_NXP_ARD_H
uint16_t * read_port16(access_word w, uint16_t *vp)
Definition: GPIO_NXP.cpp:123
const int n_bits
Definition: GPIO_NXP.h:55
void config(int port, uint8_t config, uint8_t mask=0)
Definition: GPIO_NXP.cpp:65
const int n_ports
Definition: GPIO_NXP.h:58
virtual ~GPIO_base()
Definition: GPIO_NXP.cpp:18
void write_port16(access_word w, uint16_t *vp)
Definition: GPIO_NXP.cpp:89
void output(int port, uint8_t value, uint8_t mask=0)
Definition: GPIO_NXP.cpp:40
void write_port(access_word w, uint8_t *vp)
Definition: GPIO_NXP.cpp:78
void begin(board env=NONE)
Definition: GPIO_NXP.cpp:22
uint8_t input(int port)
Definition: GPIO_NXP.cpp:53
uint8_t * read_port(access_word w, uint8_t *vp)
Definition: GPIO_NXP.cpp:110