GPIO_NXP_Arduino 0.1.0
GPIO device operation sample code for Arduino
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GPIO_NXP.h
1
8#ifndef ARDUINO_GPIO_NXP_ARD_H
9#define ARDUINO_GPIO_NXP_ARD_H
10
11#include <Arduino.h>
12#include <stdint.h>
13
14#include <I2C_device.h>
15
21enum access_word : uint8_t
22{
23 IN,
24 OUT,
25 POLARITY,
26 CONFIG,
27 DRIVE_STRENGTH,
28 LATCH,
29 PULL_UD_EN,
30 PULL_UD_SEL,
31 INT_MASK,
32 INT_STATUS,
33 OUTPUT_PORT_CONFIG,
34 NUM_access_word,
35};
36
44class GPIO_base : public I2C_device
45{
46public:
47 enum board {
48 NONE,
49 ARDUINO_SHIELD,
50 };
51
53 const int n_bits;
54
56 const int n_ports;
57
65 GPIO_base( uint8_t i2c_address, const int nbits, const uint8_t* arp, uint8_t ai );
66
68 virtual ~GPIO_base();
69
74 void begin( board env = NONE );
75
84 void output( int port, uint8_t value, uint8_t mask = 0 );
85
92 void output( uint8_t *vp );
93
101 uint8_t input( int port );
102
110 uint8_t* input( uint8_t *vp );
111
120 void config( int port, uint8_t config, uint8_t mask = 0 );
121
128 void config( uint8_t* vp );
129
137 void write_port( access_word w, uint8_t* vp );
138
146 void write_port16( access_word w, uint16_t* vp );
147
156 uint8_t* read_port( access_word w, uint8_t* vp );
157
166 uint16_t* read_port16( access_word w, uint16_t* vp );
167
176 void write_port( access_word w, uint8_t value, int port_num = 0 );
177
186 void write_port16( access_word w, uint16_t value, int port_num = 0 );
187
196 uint8_t read_port( access_word w, int port_num = 0 );
197
206 uint16_t read_port16( access_word w, int port_num = 0 );
207
208 static void print_bin( uint8_t v );
209
210private:
211 const uint8_t* arp;
212 const uint8_t auto_increment;
213 bool endian;
214
215 static constexpr int RESET_PIN = 8;
216 static constexpr int ADDR_PIN = 9;
217};
218
227{
228public:
229 PCAL6xxx_base( uint8_t i2c_address, const int nbits, const uint8_t arp[], uint8_t ai );
230 virtual ~PCAL6xxx_base();
231};
232
233
239{
240public:
242 enum reg_num {
243 Input_Port,
244 Output_Port,
245 Polarity_Inversion,
246 Configuration,
247 Output_drive_strength_0 = 0x40,
248 Output_drive_strength_1,
249 Input_latch,
250 Pull_up_pull_down_enable,
251 Pull_up_pull_down_selection,
252 Interrupt_mask,
253 Interrupt_status,
254 Output_port_configuration,
255 };
256
257 PCAL6408A( uint8_t i2c_address = (0x40 >> 1) + 0 );
258 virtual ~PCAL6408A();
259
260 static constexpr uint8_t access_ref[ NUM_access_word ] = {
261 Input_Port, // IN,
262 Output_Port, // OUT
263 Polarity_Inversion, // POLARITY
264 Configuration, // CONFIG
265 Output_drive_strength_0, // DRIVE_STRENGTH
266 Input_latch, // LATCHLATCH
267 Pull_up_pull_down_enable, // PULL_UD_EN
268 Pull_up_pull_down_selection, // PULL_UD_SEL
269 Interrupt_mask, // INT_MASK
270 Interrupt_status, // INT_STATUS
271 Output_port_configuration, // OUTPUT_PORT_CONFIG
272 };
273};
274
280{
281public:
283 enum reg_num {
284 Input_Port_0, Input_Port_1,
285 Output_Port_0, Output_Port_1,
286 Polarity_Inversion_port_0, Polarity_Inversion_port_1,
287 Configuration_port_0, Configuration_port_1,
288 Output_drive_strength_register_0=0x40, Output_drive_strength_register_0B,
289 Output_drive_strength_register_1, Output_drive_strength_register_1B,
290 Input_latch_register_0, Input_latch_register_1,
291 Pull_up_pull_down_enable_register_0, Pull_up_pull_down_enable_register_1,
292 Pull_up_pull_down_selection_register_0, Pull_up_pull_down_selection_register_1,
293 Interrupt_mask_register_0, Interrupt_mask_register_1,
294 Interrupt_status_register_0, Interrupt_status_register_1,
295 Output_port_configuration_register,
296 };
297
298 PCAL6416A( uint8_t i2c_address = (0x40 >> 1) + 0 );
299 virtual ~PCAL6416A();
300
301 static constexpr uint8_t access_ref[ NUM_access_word ] = {
302 Input_Port_0, // IN,
303 Output_Port_0, // OUT
304 Polarity_Inversion_port_0, // POLARITY
305 Configuration_port_0, // CONFIG
306 Output_drive_strength_register_0, // DRIVE_STRENGTH
307 Input_latch_register_0, // LATCHLATCH
308 Pull_up_pull_down_enable_register_0, // PULL_UD_EN
309 Pull_up_pull_down_selection_register_0, // PULL_UD_SEL
310 Interrupt_mask_register_0, // INT_MASK
311 Interrupt_status_register_0, // INT_STATUS
312 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
313 };
314};
315
321{
322public:
324 enum reg_num {
325 Input_Port_0, Input_Port_1, Input_Port_2, reserved0,
326 Output_Port_0, Output_Port_1, Output_Port_2, reserved1,
327 Polarity_Inversion_port_0, Polarity_Inversion_port_1, Polarity_Inversion_port_2, reserved2,
328 Configuration_port_0, Configuration_port_1, Configuration_port_2,
329 Output_drive_strength_register_port_0A=0x40, Output_drive_strength_register_port_0B,
330 Output_drive_strength_register_port_1A, Output_drive_strength_register_port_1B,
331 Output_drive_strength_register_port_2A, Output_drive_strength_register_port_2B,
332 reserved3, reserved4,
333 Input_latch_register_port_0, Input_latch_register_port_1, Input_latch_register_port_2, reserved5,
334 Pull_up_pull_down_enable_register_port_0, Pull_up_pull_down_enable_register_port_1, Pull_up_pull_down_enable_register_port_2, reserved6,
335 Pull_up_pull_down_selection_register_port_0, Pull_up_pull_down_selection_register_port_1, Pull_up_pull_down_selection_register_port_2, reserved7,
336 Interrupt_mask_register_port_0, Interrupt_mask_register_port_1, Interrupt_mask_register_port_2, reserved8,
337 Interrupt_status_register_port_0, Interrupt_status_register_port_1, Interrupt_status_register_port_2, reserved9,
338 Output_port_configuration_register, reserved10, reserved11, reserved12,
339 Interrupt_edge_register_port_0A, Interrupt_edge_register_port_0B,
340 Interrupt_edge_register_port_1A, Interrupt_edge_register_port_1B,
341 Interrupt_edge_register_port_2A, Interrupt_edge_register_port_2B,
342 reserved13, reserved14,
343 Interrupt_clear_register_port_0, Interrupt_clear_register_port_1, Interrupt_clear_register_port_2, reserved15,
344 Input_status_port_0, Input_status_port_1, Input_status_port_2, reserved16,
345 Individual_pin_output_port_0_configuration_register, Individual_pin_output_port_1_configuration_register, Individual_pin_output_port_2_configuration_register, reserved17,
346 Switch_debounce_enable_0, Switch_debounce_enable_1, Switch_debounce_count,
347 };
348
349 PCAL6524( uint8_t i2c_address = (0x44 >> 1) + 0 );
350 virtual ~PCAL6524();
351
352 static constexpr uint8_t access_ref[ NUM_access_word ] = {
353 Input_Port_0, // IN,
354 Output_Port_0, // OUT
355 Polarity_Inversion_port_0, // POLARITY
356 Configuration_port_0, // CONFIG
357 Output_drive_strength_register_port_0A, // DRIVE_STRENGTH
358 Input_latch_register_port_0, // LATCHLATCH
359 Pull_up_pull_down_enable_register_port_0, // PULL_UD_EN
360 Pull_up_pull_down_selection_register_port_0, // PULL_UD_SEL
361 Interrupt_mask_register_port_0, // INT_MASK
362 Interrupt_status_register_port_0, // INT_STATUS
363 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
364 };
365};
366
372{
373public:
375 enum reg_num {
376 Input_Port_0, Input_Port_1, Input_Port_2, Input_Port_3, Input_Port_4,
377 Output_Port_0, Output_Port_1, Output_Port_2, Output_Port_3, Output_Port_4,
378 Polarity_Inversion_port_0, Polarity_Inversion_port_1, Polarity_Inversion_port_2, Polarity_Inversion_port_3, Polarity_Inversion_port_4,
379 Configuration_port_0, Configuration_port_1, Configuration_port_2, Configuration_port_3, Configuration_port_4,
380 Output_drive_strength_register_port_0A = 0x30, Output_drive_strength_register_port_0B,
381 Output_drive_strength_register_port_1A, Output_drive_strength_register_port_1B,
382 Output_drive_strength_register_port_2A, Output_drive_strength_register_port_2B,
383 Output_drive_strength_register_port_3A, Output_drive_strength_register_port_3B,
384 Output_drive_strength_register_port_4A, reserved0,
385 Input_latch_register_port_0, Input_latch_register_port_1, Input_latch_register_port_2, Input_latch_register_port_3, Input_latch_register_port_4,
386 Pull_up_pull_down_enable_register_port_0, Pull_up_pull_down_enable_register_port_1, Pull_up_pull_down_enable_register_port_2, Pull_up_pull_down_enable_register_port_3, Pull_up_pull_down_enable_register_port_4,
387 Pull_up_pull_down_selection_register_port_0, Pull_up_pull_down_selection_register_port_1, Pull_up_pull_down_selection_register_port_2, Pull_up_pull_down_selection_register_port_3, Pull_up_pull_down_selection_register_port_4,
388 Interrupt_mask_register_port_0, Interrupt_mask_register_port_1, Interrupt_mask_register_port_2, Interrupt_mask_register_port_3, Interrupt_mask_register_port_4,
389 Interrupt_status_register_port_0, Interrupt_status_register_port_1, Interrupt_status_register_port_2, Interrupt_status_register_port_3, Interrupt_status_register_port_4,
390 Output_port_configuration_register,
391 Interrupt_edge_register_port_0A, Interrupt_edge_register_port_0B,
392 Interrupt_edge_register_port_1A, Interrupt_edge_register_port_1B,
393 Interrupt_edge_register_port_2A, Interrupt_edge_register_port_2B,
394 Interrupt_edge_register_port_3A, Interrupt_edge_register_port_3B,
395 Interrupt_edge_register_port_4A, reserved1,
396 Interrupt_clear_register_port_0, Interrupt_clear_register_port_1, Interrupt_clear_register_port_2, Interrupt_clear_register_port_3, Interrupt_clear_register_port_4,
397 Input_status_port_0, Input_status_port_1, Input_status_port_2, Input_status_port_3, Input_status_port_4,
398 Individual_pin_output_port_0_configuration_register, Individual_pin_output_port_1_configuration_register, Individual_pin_output_port_2_configuration_register, Individual_pin_output_port_3_configuration_register, Individual_pin_output_port_4_configuration_register,
399 Switch_debounce_enable_0, Switch_debounce_enable_1,
400 Switch_debounce_count,
401 };
402
403 PCAL6534( uint8_t i2c_address = (0x44 >> 1) + 0 );
404 virtual ~PCAL6534();
405
406 static constexpr uint8_t access_ref[ NUM_access_word ] = {
407 Input_Port_0, // IN,
408 Output_Port_0, // OUT
409 Polarity_Inversion_port_0, // POLARITY
410 Configuration_port_0, // CONFIG
411 Output_drive_strength_register_port_0A, // DRIVE_STRENGTH
412 Input_latch_register_port_0, // LATCHLATCH
413 Pull_up_pull_down_enable_register_port_0, // PULL_UD_EN
414 Pull_up_pull_down_selection_register_port_0, // PULL_UD_SEL
415 Interrupt_mask_register_port_0, // INT_MASK
416 Interrupt_status_register_port_0, // INT_STATUS
417 Output_port_configuration_register, // OUTPUT_PORT_CONFIG
418 };
419};
420
421#endif // ARDUINO_GPIO_NXP_ARD_H
uint16_t * read_port16(access_word w, uint16_t *vp)
Definition: GPIO_NXP.cpp:129
const int n_bits
Definition: GPIO_NXP.h:53
void config(int port, uint8_t config, uint8_t mask=0)
Definition: GPIO_NXP.cpp:71
const int n_ports
Definition: GPIO_NXP.h:56
virtual ~GPIO_base()
Definition: GPIO_NXP.cpp:18
void write_port16(access_word w, uint16_t *vp)
Definition: GPIO_NXP.cpp:95
void output(int port, uint8_t value, uint8_t mask=0)
Definition: GPIO_NXP.cpp:46
void write_port(access_word w, uint8_t *vp)
Definition: GPIO_NXP.cpp:84
void begin(board env=NONE)
Definition: GPIO_NXP.cpp:22
uint8_t input(int port)
Definition: GPIO_NXP.cpp:59
uint8_t * read_port(access_word w, uint8_t *vp)
Definition: GPIO_NXP.cpp:116