AFE_NXP_Arduino 2.0.5 Analog Front-End (AFE) device operation sample code for Arduino

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AFE_NXP.cpp
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1
9#include "AFE_NXP.h"
10#include <math.h>
11
12 double AFE_base::delay_accuracy = 1.1;
13
14 void LogicalChannel_Base::enable( void )
15{
16 afe_ptr->enable_logical_channel( ch_number );
17}
18
19 void LogicalChannel_Base::disable( void )
20{
21 afe_ptr->close_logical_channel( ch_number );
22}
23
24 template<>
25 AFE_base::raw_t LogicalChannel_Base::read( void )
26{
27 return afe_ptr->start_and_read( ch_number );
28}
29
30 template<>
31 AFE_base::volt_t LogicalChannel_Base::read( void )
32{
33 AFE_base::raw_t v = read<AFE_base::raw_t>();
34 return afe_ptr->raw2v( ch_number, v );
35}
36
37 LogicalChannel_Base::operator AFE_base::raw_t( void )
38{
39 return read<AFE_base::raw_t>();
40}
41
42 LogicalChannel_Base::operator AFE_base::volt_t( void )
43{
44 return read<AFE_base::volt_t>();
45}
46
47 NAFE13388_Base::LogicalChannel::LogicalChannel() : LogicalChannel_Base()
48{
49}
50
51 NAFE13388_Base::LogicalChannel::~LogicalChannel()
52{
53 disable();
54}
55
56 void NAFE13388_Base::LogicalChannel::configure( const uint16_t (&cc)[ 4 ] )
57{
58 afe_ptr->open_logical_channel( ch_number, cc );
59}
60
61 void NAFE13388_Base::LogicalChannel::configure( uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
62{
63 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
64 afe_ptr->open_logical_channel( ch_number, tmp_ch_config );
65}
66
67
68/* AFE_base class ******************************************/
69
70 AFE_base::AFE_base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC ) :
71 dev_add( spi_addr ), highspeed_variant( hsv ), pin_nINT( nINT ), pin_DRDY( DRDY ), pin_SYN( SYN ), pin_nRESET( nRESET ), pin_DRDY_input( DRDY_input ), pin_SYNCDAC( SYNCDAC ), enabled_channels( 0 )
72{
73 pinMode( pin_nINT, INPUT );
74 pinMode( pin_DRDY, INPUT );
75 pinMode( pin_DRDY_input,INPUT_PULLUP );
76 pinMode( pin_SYN, OUTPUT );
77 pinMode( pin_nRESET, OUTPUT );
78 pinMode( pin_SYNCDAC, OUTPUT );
79
80 digitalWrite( pin_SYN, 1 );
81 digitalWrite( pin_nRESET, 1 );
82}
83
84 AFE_base::~AFE_base()
85{
86}
87
88 void AFE_base::init( void )
89{
90 attachInterrupt( digitalPinToInterrupt( pin_DRDY_input ), DRDY_cb, CHANGE );
91
92 drdy_flag = false;
93 set_DRDY_callback( static_default_drdy_cb );
94
95 use_DRDY_trigger( false );
96}
97
98 void AFE_base::begin( void )
99{
100 instance = this;
101
102 SPI_for_AFE::init(); // set proper SPI_CS = HIGH state. This is required for UNO R4
103
104 reset();
105 boot();
106 init();
107}
108
109 void AFE_base::set_DRDY_callback( callback_fp_t func )
110{
111 cbf_DRDY = func;
112}
113
114 void AFE_base::DRDY_cb( void )
115{
116 if ( cbf_DRDY )
117 cbf_DRDY();
118}
119
120 void AFE_base::static_default_drdy_cb( void )
121{
122 if ( nullptr != instance )
123 instance->default_drdy_cb();
124}
125
126 void AFE_base::default_drdy_cb( void )
127{
128 drdy_count++;
129 drdy_flag = true;
130}
131
132int32_t AFE_base::start_and_read( int ch )
133{
134 double wait_time = cbf_DRDY ? -1.0 : ch_delay[ ch ] * delay_accuracy;
135
136 start( ch );
137 wait_conversion_complete( wait_time );
138
139 return read( ch );
140};
141
142#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
143 void AFE_base::start_and_read( raw_t* data )
144{
145 double wait_time = cbf_DRDY ? -1.0 : total_delay * delay_accuracy;
146
147 start();
148 wait_conversion_complete( wait_time );
149
150 read( data );
151};
152 template void AFE_base::start_and_read( raw_t* data );
153#endif
154
155 int AFE_base::bit_count( uint32_t value )
156{
157 constexpr int bit_length = 32;
158 int count = 0;
159
160 for ( int i = 0; i < bit_length; i++ ) {
161 if ( value & (0x1 << i) )
162 count++;
163 }
164
165 return count;
166}
167
168 int AFE_base::wait_conversion_complete( double wait )
169{
170 if ( 0 < wait )
171 {
172 if ( wait < 0.016 )
173 delayMicroseconds( wait * delay_accuracy * 1e6 );
174 else
175 delay( wait * delay_accuracy * 1e3 );
176 return 0;
177 }
178
179 auto timeout_count = timeout_limit;
180
181 while ( !drdy_flag && --timeout_count )
182 ;
183
184 drdy_flag = false;
185
186 if ( !timeout_count )
187 {
188 printf( "DRDY signal wait timeout\r\n" );
189 return -1;
190 }
191 return 0;
192}
193
194 void AFE_base::use_DRDY_trigger( bool use )
195{
196 if ( use )
197 set_DRDY_callback( static_default_drdy_cb );
198 else
199 set_DRDY_callback( nullptr );
200}
201
202
203 AFE_base* AFE_base::instance = nullptr;
204 AFE_base::callback_fp_t AFE_base::cbf_DRDY = nullptr;
205
206/* NAFE13388_Base class ******************************************/
207
208 NAFE13388_Base::NAFE13388_Base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
209 : AFE_base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
210{
211 for ( auto i = 0; i < 16; i++ )
212 {
213 logical_channel[ i ].afe_ptr = this;
214 logical_channel[ i ].ch_number = i;
215 }
216}
217
218 NAFE13388_Base::~NAFE13388_Base()
219{
220}
221
222 void NAFE13388_Base::boot( void )
223{
224 command( CMD_ABORT );
225 delay( 1 );
226
227 DRDY_by_sequencer_done( true );
228}
229
230 void NAFE13388_Base::reset( bool hardware_reset )
231{
232 if ( hardware_reset )
233 {
234 digitalWrite( pin_nRESET, 0 );
235 delay( 1 );
236 digitalWrite( pin_nRESET, 1 );
237 }
238 else
239 {
240 command( CMD_RESET );
241 }
242
243 constexpr uint16_t CHIP_READY = 1 << 13;
244 constexpr auto RETRY = 10;
245
246 for ( auto i = 0; i < RETRY; i++ )
247 {
248 delay( 3 );
249 if ( reg( Register16::SYS_STATUS0 ) & CHIP_READY )
250 return;
251 }
252
253 Serial.println( "NAFE13388 couldn't get ready. Check power supply or pin connections\r\n" );
254
255 while ( true )
256 ;
257}
258
259 void NAFE13388_Base::open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] )
260{
261 command( ch );
262
263 if ( cc[ 0 ] & 0x0010 )
264 {
265 coeff_V[ ch ] = ((10.0 / (double)(1L << 24)) / pga_gain[ (cc[ 0 ] >> 5) & 0x7 ]);
266 mux_setting[ ch ] = HV_MUX;
267 }
268 else
269 {
270 coeff_V[ ch ] = ((10.0 / (double)(1L << 24)) / 2.5);
271 mux_setting[ ch ] = (cc[ 0 ] >> 1) & 0x7;
272 }
273
274 for ( auto i = 0; i < 4; i++ )
275 reg( Register16::CH_CONFIG0 + i, cc[ i ] );
276
277 enable_logical_channel( ch );
278
279 ch_delay[ ch ] = calc_delay( ch );
280}
281
282 void NAFE13388_Base::channel_info_update( uint16_t value )
283{
284 constexpr auto bit_length = 16;
285 enabled_channels = 0;
286 total_delay = 0.00;
287
288 memset( sequence_order, 0, 16 );
289
290 for ( auto i = 0; i < bit_length; i++ )
291 {
292 if ( value & (0x1 << i) )
293 {
294 sequence_order[ enabled_channels ] = i;
295 enabled_channels++;
296 total_delay += ch_delay[ i ];
297 }
298 }
299
300#if 0
301 for ( auto i = 0; i < bit_length; i++ )
302 printf( " %x", sequence_order[ i ] );
303 printf( "\r\n" );
304#endif
305}
306
307 double NAFE13388_Base::calc_delay( int ch )
308{
309 constexpr static double data_rates[] = { 288000, 192000, 144000, 96000, 72000, 48000, 36000, 24000,
310 18000, 12000, 9000, 6000, 4500, 3000, 2250, 1125,
311 562.5, 400, 300, 200, 100, 60, 50, 30,
312 25, 20, 15, 10, 7.5, };
313 constexpr static uint16_t delays[] = { 0, 2, 4, 6, 8, 10, 12, 14,
314 16, 18, 20, 28, 38, 40, 42, 56,
315 64, 76, 90, 128, 154, 178, 204, 224,
316 256, 358, 512, 716,
317 1024, 1664, 3276, 7680, 19200, 23040, };
318
319 command( ch );
320
321 uint16_t ch_config1 = reg( Register16::CH_CONFIG1 );
322 uint16_t ch_config2 = reg( Register16::CH_CONFIG2 );
323
324 uint8_t adc_data_rate = (ch_config1 >> 3) & 0x001F;
325 uint8_t adc_sinc = (ch_config1 >> 0) & 0x0007;
326 uint8_t ch_delay = (ch_config2 >> 10) & 0x003F;
327 bool adc_normal_setting = (ch_config2 >> 9) & 0x0001;
328 bool ch_chop = (ch_config2 >> 7) & 0x0001;
329
330 double base_freq = data_rates[ adc_data_rate ];
331 double delay_setting = delays[ ch_delay ] / 4608000.00;
332
333 if ( highspeed_variant )
334 {
335 base_freq *= 2.00;
336 delay_setting /= 2.00;
337 }
338
339 if ( (28 < adc_data_rate) || (4 < adc_sinc) || ((adc_data_rate < 12) && (adc_sinc)) )
340 return 0.00;
341
342 if ( !adc_normal_setting )
343 base_freq /= (adc_sinc + 1);
344
345 if ( ch_chop )
346 base_freq /= 2;
347
348#if 0
349 printf( "base_freq = %lf\r\n", base_freq );
350 printf( "delay_setting = %lf\r\n", delay_setting );
351 printf( "total delay = %lf\r\n", (1 / base_freq) + delay_setting );
352#endif
353
354 return (1 / base_freq) + delay_setting;
355}
356
357 void NAFE13388_Base::open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
358{
359 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
360 open_logical_channel( ch, tmp_ch_config );
361}
362
363 void NAFE13388_Base::enable_logical_channel( int ch )
364{
365 const uint16_t setbit = 0x1 << ch;
366 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~setbit, setbit );
367
368 channel_info_update( bits );
369}
370
371 void NAFE13388_Base::close_logical_channel( int ch )
372{
373 const uint16_t clearingbit = 0x1 << ch;
374 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~clearingbit, ~clearingbit );
375
376 channel_info_update( bits );
377}
378
379 void NAFE13388_Base::close_logical_channel( void )
380{
381 reg( Register16::CH_CONFIG4, 0x0000 );
382 channel_info_update( 0x0000 );
383}
384
385 void NAFE13388_Base::start( int ch )
386{
387 command( ch );
388 command( Command::CMD_SS );
389}
390
391 void NAFE13388_Base::start( void )
392{
393 command( Command::CMD_MM );
394}
395
396 void NAFE13388_Base::start_continuous_conversion( void )
397{
398 command( Command::CMD_MC );
399}
400
401 void NAFE13388_Base::DRDY_by_sequencer_done( bool flag )
402{
403 bit_op( Register16::SYS_CONFIG0, ~0x0010, flag ? 0x0010 : 0x00 );
404}
405
406int32_t NAFE13388_Base::read( int ch )
407{
408 return reg( Register24::CH_DATA0 + ch );
409}
410
411 void NAFE13388_Base::read( raw_t *data )
412{
413 burst( (uint32_t *)data, enabled_channels );
414}
415
416 void NAFE13388_Base::read( volt_t *data )
417{
418 raw_t raw_data[ 16 ];
419
420 read( raw_data );
421
422 for ( auto i = 0; i < enabled_channels; i++ )
423 data[ i ] = raw2v( sequence_order[ i ], raw_data[ i ] );
424}
425
426 void NAFE13388_Base::command( uint16_t com )
427{
428 write_r16( com );
429}
430
431 void NAFE13388_Base::reg( Register16 r, uint16_t value )
432{
433 write_r16( static_cast<uint16_t>( r ), value );
434}
435
436 void NAFE13388_Base::reg( Register24 r, uint32_t value )
437{
438 write_r24( static_cast<uint16_t>( r ), value );
439}
440
441uint16_t NAFE13388_Base::reg( Register16 r )
442{
443 return read_r16( static_cast<uint16_t>( r ) );
444}
445
446uint32_t NAFE13388_Base::reg( Register24 r )
447{
448 return read_r24( static_cast<uint16_t>( r ) );
449}
450
451uint32_t NAFE13388_Base::part_number( void )
452{
453 return (static_cast<uint32_t>( reg( Register16::PN2 ) ) << 16) | reg( Register16::PN1 );
454}
455
456uint8_t NAFE13388_Base::revision_number( void )
457{
458 return reg( Register16::PN0 ) & 0xF;
459}
460
461uint64_t NAFE13388_Base::serial_number( void )
462{
463 uint64_t serial_number;
464
465 serial_number = reg( Register24::SERIAL1 );
466 serial_number <<= 24;
467 return serial_number | reg( Register24::SERIAL0 );
468}
469
470 float NAFE13388_Base::temperature( void )
471{
472 return ((int16_t)reg( Register16::DIE_TEMP )) / 64.0;
473}
474
475 void NAFE13388_Base::gain_offset_coeff( const ref_points &ref )
476{
477 constexpr double pga1x_voltage = 5.0;
478 constexpr int adc_resolution = 24;
479 constexpr double pga_gain_setting = 0.2;
480
481 constexpr double fullscale_voltage = pga1x_voltage / pga_gain_setting;
482
483 double fullscale_data = pow( 2, (adc_resolution - 1) );
484 double ref_data_span = ref.high.data - ref.low.data;
485 double ref_voltage_span = ref.high.voltage - ref.low.voltage;
486
487 double dv_slope = ref_data_span / ref_voltage_span;
488 double custom_gain = dv_slope * (fullscale_voltage / fullscale_data);
489 double custom_offset = (dv_slope * ref.low.voltage - ref.low.data) / custom_gain;
490
491 int32_t gain_coeff_cal = reg( Register24::GAIN_COEFF0 + ref.cal_index );
492 int32_t offsset_coeff_cal = reg( Register24::OFFSET_COEFF0 + ref.cal_index );
493 int32_t gain_coeff_new = round( gain_coeff_cal * custom_gain );
494 int32_t offset_coeff_new = round( custom_offset - offsset_coeff_cal );
495
496#if 0
497 printf( "ref_point_high = %8ld @%6.3lf\r\n", ref.high.data, ref.high.voltage );
498 printf( "ref_point_low = %8ld @%6.3lf\r\n", ref.low.data, ref.low.voltage );
499 printf( "gain_coeff_new = %8ld\r\n", gain_coeff_new );
500 printf( "offset_coeff_new = %8ld\r\n", offset_coeff_new );
501#endif
502
503 reg( Register24::GAIN_COEFF0 + ref.coeff_index, gain_coeff_new );
504 reg( Register24::OFFSET_COEFF0 + ref.coeff_index, offset_coeff_new );
505}
506
507 int NAFE13388_Base::self_calibrate( int pga_gain_index, int channel_selection, int input_select, double reference_source_voltage, bool use_positive_side )
508{
509 constexpr auto low_gain_index = 2;
510 auto channel_in_use = false;
511 ch_setting_t tmp_ch_config;
512 int gain_index = static_cast<int>( pga_gain_index );
513
514 // logical channel selection to perform the self-calibration
515 // if the channel in-use, save channel setting to temporal memory
516
517 if ( reg( Register16::CH_CONFIG4 ) & (0x1 << channel_selection) )
518 {
519 channel_in_use = true;
520
521 command( channel_selection );
522
523 for ( auto i = 0; i < 4; i++ )
524 tmp_ch_config[ i ] = reg( Register16::CH_CONFIG0 + i );
525 }
526
527 // if user doesn't specify the channel and voltage, use REFH or REFL
528
529 if ( !input_select )
530 {
531 bool low_gain = (gain_index <= low_gain_index);
532
533 input_select = low_gain ? 0x5 : 0x6;
534 reference_source_voltage = (reg( low_gain ? Register24::OPT_COEF1 : Register24::OPT_COEF2 ) * 5.00) / (double)(1UL << 24);
535
536#if 1
537 printf( "==== self-calibration for PGA gain setting: x%3.1lf\r\n", pga_gain[ gain_index ] );
538 printf( "gain = %s\r\n", low_gain ? "low" : "high" );
539 printf( "REF%s = %10.8lfV\r\n", low_gain ? "H" : "L", reference_source_voltage );
540#endif
541 }
542
543 // logical channel settings
544 // Total 3 settings are prepared to measure reference_voltage, internal-GND and AICOM
545
546 const uint16_t REF_GND = 0x0011 | (gain_index << 5);
547 const uint16_t REF_V = (input_select << (use_positive_side ? 12 : 8)) | REF_GND;
548 const uint16_t REF_COM = 0x7700 | REF_GND;
549 const uint16_t ch_config1 = (gain_index << 12) | 0x00E4;
550 constexpr uint16_t ch_config2 = 0x8480;
551 constexpr uint16_t ch_config3 = 0x0000;
552
553 const ch_setting_t refh = { REF_V, ch_config1, ch_config2, ch_config3 };
554 const ch_setting_t refg = { REF_GND, ch_config1, ch_config2, ch_config3 };
555 const ch_setting_t refc = { REF_COM, ch_config1, ch_config2 & ~0x0080, ch_config3 }; //CH_CHOP:off
556
557 // forcing to set unity-gain and zero-offset
558
559 constexpr raw_t default_gain_coeff_value = 0x1UL << 22;
560 constexpr raw_t default_offset_coeff_value = 0;
561
562 reg( Register24::GAIN_COEFF0 + gain_index, default_gain_coeff_value );
563 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value );
564
565 // measure the logical channel with those different 3 settings
566
567 open_logical_channel( channel_selection, refh );
568 raw_t data_REF = start_and_read( channel_selection );
569
570 open_logical_channel( channel_selection, refg );
571 raw_t data_GND = start_and_read( channel_selection );
572
573 open_logical_channel( channel_selection, refc );
574 raw_t data_COM = start_and_read( channel_selection );
575
576 // calculation
577
578 const double fullscale_voltage = 5.00 / pga_gain[ gain_index ];
579 const double calibrated_gain = (double)(0x1UL << 23) * (reference_source_voltage / fullscale_voltage) / (double)(data_REF - data_GND);
580
581#if 0
582 printf( "data_REF = %8ld (%lfV)\r\n", data_REF, raw2v( channel_selection, data_REF ) );
583 printf( "data_GND = %8ld (%lfmV)\r\n", data_GND, raw2mv( channel_selection, data_GND ) );
584 printf( "data_COM = %8ld (%lfmV)\r\n", data_COM, raw2mv( channel_selection, data_COM ) );
585 printf( "gain adjustment = %8lf (%lfdB)\r\n\r\n", calibrated_gain, 20 * log10( calibrated_gain ) );
586#endif
587
588 if ( !( (0.95 < calibrated_gain) && (calibrated_gain < 1.05) ) )
589 return CalibrationError::GainError;
590
591 const double offset_mv = raw2mv( channel_selection, data_COM );
592
593 if ( !( (-10.0 < offset_mv) && (offset_mv < 10.0) ) )
594 return CalibrationError::OffsetError;
595
596 // setting registers: GAIN_COEFF[n] and OFFSET_COEFF[n]
597
598 reg( Register24::GAIN_COEFF0 + gain_index, (uint32_t)(default_gain_coeff_value * calibrated_gain) );
599 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value + data_COM );
600
601 // if the channel was in-use, revert the setting
602
603 if ( channel_in_use )
604 open_logical_channel( channel_selection, tmp_ch_config );
605 else
606 close_logical_channel( channel_selection );
607
608 return CalibrationError::NoError;
609}
610
611 void NAFE13388_Base::blink_leds( void )
612{
613}
614
615
616/* NAFE13388 class ******************************************/
617
618 NAFE13388::NAFE13388( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
619 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
620{
621}
622
623 NAFE13388::~NAFE13388()
624{
625}
626
627/* NAFE13388_UIM class ******************************************/
628
629 NAFE13388_UIM::NAFE13388_UIM( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
630 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
631{
632}
633
634 NAFE13388_UIM::~NAFE13388_UIM()
635{
636}
637
638 void NAFE13388_UIM::blink_leds( void )
639{
640 uint16_t pattern[] = {
641 0x8000, 0x0040, 0x0100, 0x0080, 0x0200, 0x0400, 0x0800, 0x1000,
642 0x2000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0080,
643 0x0100, 0x0040,
644 };
645 reg( Register16::GPIO_CONFIG0, 0xFFC0 );
646 reg( Register16::GPIO_CONFIG1, 0xFFC0 );
647 reg( Register16::GPIO_CONFIG2, 0x0000 );
648
649 for ( auto j = 0; j < 2; j++ )
650 {
651 for ( auto i = 0U; i < sizeof( pattern ) / sizeof( uint16_t ); i++ )
652 {
653 reg( Register16::GPO_DATA, pattern[ i ] );
654 delay( 20 );
655 }
656 }
657
658 uint16_t pv = 0;
659
660 for ( auto j = 0; j < 4; j++ )
661 {
662 for ( auto i = 0; i < 10; i++ )
663 {
664 pv = (j % 2) ? pv & ~pattern[ i ] : pv | pattern[ i ];
665 reg( Register16::GPO_DATA, pv ); delay( 20 );
666 }
667 }
668}
669
670 double NAFE13388_Base::pga_gain[] = { 0.2, 0.4, 0.8, 1, 2, 4, 8, 16 };
671
AFE_NXP.h
AFE_base
Definition AFE_NXP.h:18
AFE_base::enable_logical_channel
virtual void enable_logical_channel(int ch)=0
AFE_base::instance
static AFE_base * instance
Definition AFE_NXP.h:277
AFE_base::cbf_DRDY
static callback_fp_t cbf_DRDY
Definition AFE_NXP.h:263
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::volt_t
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Definition AFE_NXP.h:23
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Definition AFE_NXP.cpp:194
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Definition AFE_NXP.cpp:84
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Definition AFE_NXP.cpp:114
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Definition AFE_NXP.h:225
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Definition AFE_NXP.cpp:109
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Definition AFE_NXP.h:229
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Definition AFE_NXP.cpp:88
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Definition AFE_NXP.h:257
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Definition AFE_NXP.cpp:98
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Definition AFE_NXP.h:182
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Definition AFE_NXP.h:164
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Definition AFE_NXP.h:224
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Definition AFE_NXP.h:261
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Definition AFE_NXP.cpp:155
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Definition AFE_NXP.h:230
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Definition AFE_NXP.cpp:126
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Definition AFE_NXP.h:46
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Definition AFE_NXP.h:247
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Definition AFE_NXP.cpp:132
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Definition AFE_NXP.h:241
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Definition AFE_NXP.h:244
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Definition AFE_NXP.cpp:120
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Definition AFE_NXP.cpp:70
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Definition AFE_NXP.cpp:168
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Definition AFE_NXP.h:262
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Definition AFE_NXP.h:227
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Definition AFE_NXP.h:255
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Definition AFE_NXP.h:253
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Definition AFE_NXP.h:250
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Definition AFE_NXP.h:228
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Definition AFE_NXP.h:223
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Definition AFE_NXP.h:226
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Definition AFE_NXP.h:254
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Definition AFE_NXP.h:281
LogicalChannel_Base::read
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Definition AFE_NXP.cpp:14
LogicalChannel_Base::afe_ptr
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Definition AFE_NXP.h:314
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Definition AFE_NXP.h:313
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Definition AFE_NXP.cpp:19
NAFE13388_Base::LogicalChannel::~LogicalChannel
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Definition AFE_NXP.cpp:51
NAFE13388_Base::LogicalChannel::LogicalChannel
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Definition AFE_NXP.cpp:47
NAFE13388_Base::LogicalChannel::configure
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Definition AFE_NXP.cpp:56
NAFE13388_Base
Definition AFE_NXP.h:318
NAFE13388_Base::start_continuous_conversion
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Definition AFE_NXP.cpp:396
NAFE13388_Base::raw2v
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Definition AFE_NXP.h:451
NAFE13388_Base::boot
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Definition AFE_NXP.cpp:222
NAFE13388_Base::gain_offset_coeff
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Definition AFE_NXP.cpp:475
NAFE13388_Base::calc_delay
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Definition AFE_NXP.cpp:307
NAFE13388_Base::command
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Definition AFE_NXP.cpp:426
NAFE13388_Base::blink_leds
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Definition AFE_NXP.cpp:611
NAFE13388_Base::read
virtual raw_t read(int ch)
Definition AFE_NXP.cpp:406
NAFE13388_Base::logical_channel
LogicalChannel logical_channel[16]
Definition AFE_NXP.h:385
NAFE13388_Base::pga_gain
static double pga_gain[]
Definition AFE_NXP.h:670
NAFE13388_Base::bit_op
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Definition AFE_NXP.h:703
NAFE13388_Base::self_calibrate
int self_calibrate(int pga_gain_index, int channel_selection=15, int input_select=0, double reference_source_voltage=0, bool use_positive_side=true)
Definition AFE_NXP.cpp:507
NAFE13388_Base::start
virtual void start(void)
Definition AFE_NXP.cpp:391
NAFE13388_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition AFE_NXP.cpp:431
NAFE13388_Base::revision_number
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Definition AFE_NXP.cpp:456
NAFE13388_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition AFE_NXP.cpp:379
NAFE13388_Base::Register24
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Definition AFE_NXP.h:523
NAFE13388_Base::Register24::OFFSET_COEFF0
@ OFFSET_COEFF0
NAFE13388_Base::Register24::GAIN_COEFF0
@ GAIN_COEFF0
NAFE13388_Base::Register24::OPT_COEF2
@ OPT_COEF2
NAFE13388_Base::Register24::SERIAL0
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NAFE13388_Base::Register24::OPT_COEF1
@ OPT_COEF1
NAFE13388_Base::Register24::SERIAL1
@ SERIAL1
NAFE13388_Base::Register24::CH_DATA0
@ CH_DATA0
NAFE13388_Base::CMD_MM
@ CMD_MM
Definition AFE_NXP.h:648
NAFE13388_Base::CMD_MC
@ CMD_MC
Definition AFE_NXP.h:649
NAFE13388_Base::CMD_SS
@ CMD_SS
Definition AFE_NXP.h:646
NAFE13388_Base::CMD_RESET
@ CMD_RESET
Definition AFE_NXP.h:642
NAFE13388_Base::CMD_ABORT
@ CMD_ABORT
Definition AFE_NXP.h:638
NAFE13388_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition AFE_NXP.cpp:401
NAFE13388_Base::serial_number
uint64_t serial_number(void)
Definition AFE_NXP.cpp:461
NAFE13388_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition AFE_NXP.cpp:282
NAFE13388_Base::~NAFE13388_Base
virtual ~NAFE13388_Base()
Definition AFE_NXP.cpp:218
NAFE13388_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition AFE_NXP.cpp:363
NAFE13388_Base::reset
virtual void reset(bool hardware_reset=false)
Definition AFE_NXP.cpp:230
NAFE13388_Base::part_number
uint32_t part_number(void)
Definition AFE_NXP.cpp:451
NAFE13388_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
Definition AFE_NXP.cpp:357
NAFE13388_Base::NAFE13388_Base
NAFE13388_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition AFE_NXP.cpp:208
NAFE13388_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition AFE_NXP.h:320
NAFE13388_Base::Register16
Register16
Definition AFE_NXP.h:493
NAFE13388_Base::Register16::CH_CONFIG1
@ CH_CONFIG1
NAFE13388_Base::Register16::CH_CONFIG2
@ CH_CONFIG2
NAFE13388_Base::Register16::GPIO_CONFIG0
@ GPIO_CONFIG0
NAFE13388_Base::Register16::PN1
@ PN1
NAFE13388_Base::Register16::CH_CONFIG4
@ CH_CONFIG4
NAFE13388_Base::Register16::SYS_STATUS0
@ SYS_STATUS0
NAFE13388_Base::Register16::PN0
@ PN0
NAFE13388_Base::Register16::GPIO_CONFIG2
@ GPIO_CONFIG2
NAFE13388_Base::Register16::DIE_TEMP
@ DIE_TEMP
NAFE13388_Base::Register16::CH_CONFIG0
@ CH_CONFIG0
NAFE13388_Base::Register16::GPIO_CONFIG1
@ GPIO_CONFIG1
NAFE13388_Base::Register16::GPO_DATA
@ GPO_DATA
NAFE13388_Base::Register16::PN2
@ PN2
NAFE13388_Base::Register16::SYS_CONFIG0
@ SYS_CONFIG0
NAFE13388_Base::temperature
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Definition AFE_NXP.cpp:470
NAFE13388_Base::NoError
@ NoError
Definition AFE_NXP.h:747
NAFE13388_Base::OffsetError
@ OffsetError
Definition AFE_NXP.h:749
NAFE13388_Base::GainError
@ GainError
Definition AFE_NXP.h:748
NAFE13388_UIM::NAFE13388_UIM
NAFE13388_UIM(bool spi_addr=0, bool highspeed_variant=false, int nINT=3, int DRDY=4, int SYN=6, int nRESET=7, int DRDY_input=2, int SYNCDAC=14)
Definition AFE_NXP.cpp:629
NAFE13388_UIM::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:638
NAFE13388_UIM::~NAFE13388_UIM
virtual ~NAFE13388_UIM()
Definition AFE_NXP.cpp:634
NAFE13388::~NAFE13388
virtual ~NAFE13388()
Definition AFE_NXP.cpp:623
NAFE13388::NAFE13388
NAFE13388(bool spi_addr=0, bool highspeed_variant=false, int nINT=2, int DRDY=4, int SYN=5, int nRESET=6, int DRDY_input=15, int SYNCDAC=14)
Definition AFE_NXP.cpp:618
SPI_for_AFE::read_r24
virtual int32_t read_r24(uint16_t reg)
Definition SPI_for_AFE.cpp:48
SPI_for_AFE::init
void init(void)
Definition SPI_for_AFE.cpp:78
SPI_for_AFE::write_r24
virtual void write_r24(uint16_t reg, uint32_t val)
Definition SPI_for_AFE.cpp:40
SPI_for_AFE::read_r16
virtual uint16_t read_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:29
SPI_for_AFE::burst
virtual void burst(uint32_t *data, int length, int width=3)
Definition SPI_for_AFE.cpp:59
SPI_for_AFE::write_r16
virtual void write_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:13
NAFE13388_Base::_ref_points
Definition AFE_NXP.h:327