AFE_NXP_Arduino 2.0.5 Analog Front-End (AFE) device operation sample code for Arduino

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NAFE33352.h
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1
8
9#include <Arduino.h>
10#include "AFE_NXP.h"
11#include "SPI_for_AFE.h"
12
13#ifndef ARDUINO_AFE_NAFE33352_DRIVER_H
14#define ARDUINO_AFE_NAFE33352_DRIVER_H
15
16 class NAFE33352_Base : public AFE_base
17{
18 public:
19 using ch_setting_t = uint16_t[ 4 ];
20 static constexpr double on_board_shunt_resister = 50.00;
21
23 NAFE33352_Base( bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC );
24
26 virtual ~NAFE33352_Base();
27
28 private:
35 virtual void txrx( uint8_t *data, int size, int cs_delay = 0 );
36
42 virtual void write_r24( uint16_t reg, uint32_t val );
43
44 public:
46 virtual void boot( void );
47
49 virtual void reset( bool hardware_reset = false );
50
59 virtual void open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t dummy );
60
66 virtual void open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] );
67
69 class LogicalChannel : public LogicalChannel_Base
70 {
71 public:
72 LogicalChannel();
73 virtual ~LogicalChannel();
74
79 void configure( const uint16_t (&cc)[ 3 ] );
80
87 void configure( uint16_t cc0, uint16_t cc1 = 0x0000, uint16_t cc2 = 0x0000 );
88 };
89
91 LogicalChannel logical_channel[ 16 ];
92
94 class DAC
95 {
96 public:
97
99 enum class ModeSelect : uint16_t {
100 OFF = 0,
101 VOLTAGE,
102 CURRENT,
103 CURRENT_RECAL,
104 DAC_OFF_VOLTAGE_IN,
105 DAC_OFF_CURRENT_IN
106 };
107
108 DAC();
109 virtual ~DAC();
110
115 void configure( const uint16_t (&cc)[ 6 ] );
116
126 void configure( uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3, uint16_t cc4, uint16_t cc5 );
127
133 void configure( ModeSelect mode, double full_scale_range = 0.00 );
134
139 void configure( double full_scale_range );
140
145 void output( double value );
146
151 DAC& operator=( double value );
152
154 NAFE33352_Base *afe_ptr;
155 private:
156 ModeSelect output_mode;
157 double full_scale;
158 };
159
160 DAC dac;
161
162 private:
163 double calc_delay( int ch );
164 void channel_info_update( uint16_t value );
165
166 public:
171 void open_dac_output( const uint16_t (&cc)[ 6 ] );
172
173
178 virtual void close_logical_channel( int ch );
179
182 virtual void close_logical_channel( void );
183
188 void enable_logical_channel( int ch );
189
194 virtual void start( int ch );
195
198 virtual void start( void );
199
202 virtual void start_continuous_conversion();
203
208 virtual void DRDY_by_sequencer_done( bool flag = true );
209
214 virtual raw_t read( int ch );
215
220 virtual void read( raw_t *data );
221
226 virtual void read( volt_t *data );
227
233 inline double raw2v( int ch, raw_t value )
234 {
235 if ( mux_setting[ ch ] == ISNS )
236 return value * coeff_V[ ch ] / on_board_shunt_resister;
237 else if ( mux_setting[ ch ] == BG )
238 return value - (double)(1L << 24) * 20.00 * 2.50 / (12.50 * (double)(1L << 24)) -1.50;
239 else
240 return value * coeff_V[ ch ];
241 }
242
249 virtual void dac_out( double vi, double full_scale, uint8_t bit_length );
250
258 int32_t dac_code( double a, double full_scale, uint8_t bit_length );
259
260 constexpr static double pga_gain[] = { 1.00, 16.00 };
261
262 enum IN_SEL : uint8_t {
263 VCM_VCM = 0,
264 AIP_AIN,
265 AIP_VSNS,
266 GPIO0_GPIO1,
267 AIP,
268 AIN,
269 ISNS,
270 VSNS,
271 TIA,
272 GPIO0_VCM,
273 VCM_GPIO1,
274 REF_BYP__VCM,
275 VCM__REF_BYP,
276 BG,
277 VADD,
278 LDO,
279 VHDD,
280 VHSS,
281 DAC_REF
282 };
283
284 enum GainPGA : uint8_t {
285 G_PGA_x_1_0,
286 G_PGA_x16_0,
287 };
288
289 enum class Register16 : uint16_t {
290 CRC_CONF_REGS = 0x20,
291 CRC_COEF_REGS = 0x21,
292 CRC_TRIM_REGS = 0x22,
293 CRC_TRIM_REF = 0x3F,
294 GPI_DATA = 0x23,
295 GPO_ENABLE = 0x24,
296 GPIO_FUNCTION = 0x25,
297 GPI_ENABLE = 0x26,
298 GPI_EDGE_POS = 0x27,
299 GPI_EDGE_NEG = 0x28,
300 GPO_DATA = 0x29,
301 SYS_CONFIG = 0x2A,
302 SYS_STATUS = 0x2B,
303 CK_SRC_SEL_CONFIG = 0x30,
304 GLOBAL_ALARM_ENABLE = 0x2C,
305 GLOBAL_ALARM_INT = 0x2D,
306 DIE_TEMP = 0x2E,
307 TEMP_THRS = 0x2F,
308 PN2 = 0x40,
309 PN1 = 0x41,
310 PN0_REV = 0x42,
311
312 AI_CONFIG0 = 0x1000 | 0x20,
313 AI_CONFIG1 = 0x1000 | 0x21,
314 AI_CONFIG2 = 0x1000 | 0x22,
315 AI_MULTI_CH_EN = 0x1000 | 0x23,
316 AI_SYSCFG = 0x1000 | 0x24,
317 AI_STATUS = 0x1000 | 0x25,
318 AI_STATUS_OVR = 0x1000 | 0x26,
319 AI_STATUS_UDR = 0x1000 | 0x27,
320
321 AIO_CONFIG = 0x1C00 | 0x20,
322 AO_CAL_COEF = 0x1C00 | 0x21,
323 AIO_PROT_CFG = 0x1C00 | 0x22,
324 AO_SLR_CTRL = 0x1C00 | 0x23,
325 AWG_PER = 0x1C00 | 0x24,
326 AO_SYSCFG = 0x1C00 | 0x25,
327 AIO_STATUS = 0x1C00 | 0x26
328 };
329
330 enum class Register24 : uint16_t {
331 GAIN_COEF0 = 0x50,
332 GAIN_COEF1,
333 GAIN_COEF2,
334 GAIN_COEF3,
335 GAIN_COEF4,
336 GAIN_COEF5,
337 GAIN_COEF6,
338 GAIN_COEF7,
339 OFFSET_COEF0 = 0x58,
340 OFFSET_COEF1,
341 OFFSET_COEF2,
342 OFFSET_COEF3,
343 OFFSET_COEF4,
344 OFFSET_COEF5,
345 OFFSET_COEF6,
346 OFFSET_COEF7,
347 EXTRA_CAL_COEF0 = 0x60,
348 EXTRA_CAL_COEF1,
349 EXTRA_CAL_COEF2,
350 EXTRA_CAL_COEF3,
351 EXTRA_CAL_COEF4,
352 EXTRA_CAL_COEF5,
353 EXTRA_CAL_COEF6,
354 EXTRA_CAL_COEF7,
355 SERIAL1 = 0x43,
356 SERIAL0,
357
358 AI_DATA0 = 0x1000 | 0x30,
359 AI_DATA1,
360 AI_DATA2,
361 AI_DATA3,
362 AI_DATA4,
363 AI_DATA5,
364 AI_DATA6,
365 AI_DATA7,
366 AI_CH_OVR_THR_0 = 0x1000 | 0x38,
367 AI_CH_OVR_THR_1,
368 AI_CH_OVR_THR_2,
369 AI_CH_OVR_THR_3,
370 AI_CH_OVR_THR_4,
371 AI_CH_OVR_THR_5,
372 AI_CH_OVR_THR_6,
373 AI_CH_OVR_THR_7,
374 AI_CH_UDR_THR_0 = 0x1000 | 0x40,
375 AI_CH_UDR_THR_1,
376 AI_CH_UDR_THR_2,
377 AI_CH_UDR_THR_3,
378 AI_CH_UDR_THR_4,
379 AI_CH_UDR_THR_5,
380 AI_CH_UDR_THR_6,
381 AI_CH_UDR_THR_7,
382
383 AO_DATA = 0x1C00 | 0x28,
384 AO_OC_POS_LIMIT,
385 AO_OC_NEG_LIMIT,
386 AWG_AMP_MAX,
387 AWG_AMP_MIN
388 };
389
390 enum Command : uint16_t {
391 CMD_CLEAR_ALARM = 0x12,
392 CMD_RESET = 0x14,
393 CMD_CLEAR_REG = 0x15,
394 CMD_RELOAD = 0x16,
395 CMD_CALC_CRC_CONFIG = 0x2006,
396 CMD_CALC_CRC_COEF = 0x2007,
397 CMD_CALC_CRC_FAC = 0x2008,
398
399 CMD_CH0 = 0x1000,
400 CMD_CH1 = 0x1001,
401 CMD_CH2 = 0x1002,
402 CMD_CH3 = 0x1003,
403 CMD_CH4 = 0x1004,
404 CMD_CH5 = 0x1005,
405 CMD_CH6 = 0x1006,
406 CMD_CH7 = 0x1007,
407 CMD_ADC_ABORT = 0x1010,
408 CMD_END = 0x1012,
409 CMD_CLEAR_DATA = 0x1013,
410 CMD_SS = 0x3000,
411 CMD_SC = 0x3001,
412 CMD_MM = 0x3002,
413 CMD_MC = 0x3003,
414 CMD_MS = 0x3004,
415 CMD_BURST_DATA = 0x3005,
416
417 CMD_WGEN_STOP = 0x1C00,
418 CMD_WGEN_START = 0x1C01,
419 CMD_CLEAR_DAC0 = 0x1C02,
420 CMD_AO_ABORT = 0x1C03,
421 CMD_AO_ABORT_HIZ = 0x1C04,
422 CMD_CISW_ABORT = 0x1C05,
423 CMD_CISW_ABORT_HIZ = 0x1C06,
424 };
425
430 virtual void command( uint16_t com );
431
438 virtual void reg( Register16 r, uint16_t value );
439
446 virtual void reg( Register24 r, uint32_t value );
447
454 virtual uint16_t reg( Register16 r );
455
462 virtual uint32_t reg( Register24 r );
463
471 template<typename T>
472 uint32_t bit_op( T rg, uint32_t mask, uint32_t value )
473 {
474 uint32_t v = reg( rg );
475
476 v &= mask;
477 v |= value & ~mask;
478
479 reg( rg, v );
480
481 return v;
482 }
483
488 uint64_t part_number( void );
489
494 uint8_t revision_number( void );
495
500 uint64_t serial_number( void );
501
506 float temperature( void );
507};
508
509 class NAFE33352 : public NAFE33352_Base
510{
511 public:
513 NAFE33352( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 7, int DRDY = 4, int SYN = 14, int nRESET = 14, int DRDY_input = 2, int SYNCDAC = 14 );
514
516 virtual ~NAFE33352();
517};
518
519 class NAFE33352_UIOM : public NAFE33352_Base
520{
521 public:
523 NAFE33352_UIOM( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 7, int DRDY = 4, int SYN = 14, int nRESET = 14, int DRDY_input = 2, int SYNCDAC = 14 );
524
526 virtual ~NAFE33352_UIOM();
527};
528
529
530 inline NAFE33352_Base::Register16 operator+( NAFE33352_Base::Register16 rn, int n )
531{
532 return static_cast<NAFE33352_Base::Register16>( static_cast<uint16_t>( rn ) + n );
533}
534
535 inline NAFE33352_Base::Register16 operator+( int n, NAFE33352_Base::Register16 rn )
536{
537 return static_cast<NAFE33352_Base::Register16>( n + static_cast<uint16_t>( rn ) );
538}
539
540 inline NAFE33352_Base::Register24 operator+( NAFE33352_Base::Register24 rn, int n )
541{
542 return static_cast<NAFE33352_Base::Register24>( static_cast<uint16_t>( rn ) + n );
543}
544
545 inline NAFE33352_Base::Register24 operator+( int n, NAFE33352_Base::Register24 rn )
546{
547 return static_cast<NAFE33352_Base::Register24>( n + static_cast<uint16_t>( rn ) );
548}
549
550#endif // !ARDUINO_AFE_NAFE33352_DRIVER_H
AFE_NXP.h
operator+
NAFE33352_Base::Register16 operator+(NAFE33352_Base::Register16 rn, int n)
Definition NAFE33352.h:530
SPI_for_AFE.h
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::volt_t
double volt_t
Definition AFE_NXP.h:23
AFE_base::highspeed_variant
bool highspeed_variant
Definition AFE_NXP.h:224
AFE_base::coeff_V
double coeff_V[16]
Definition AFE_NXP.h:247
AFE_base::AFE_base
AFE_base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition AFE_NXP.cpp:70
AFE_base::mux_setting
int mux_setting[16]
Definition AFE_NXP.h:250
LogicalChannel_Base::LogicalChannel_Base
LogicalChannel_Base()
Definition AFE_NXP.h:283
NAFE33352_Base::DAC
Definition NAFE33352.h:95
NAFE33352_Base::DAC::afe_ptr
NAFE33352_Base * afe_ptr
Definition NAFE33352.h:154
NAFE33352_Base::DAC::operator=
DAC & operator=(double value)
Definition NAFE33352.cpp:105
NAFE33352_Base::DAC::output_mode
ModeSelect output_mode
Definition NAFE33352.h:156
NAFE33352_Base::DAC::full_scale
double full_scale
Definition NAFE33352.h:157
NAFE33352_Base::DAC::DAC
DAC()
Definition NAFE33352.cpp:34
NAFE33352_Base::DAC::output
void output(double value)
Definition NAFE33352.cpp:100
NAFE33352_Base::DAC::~DAC
virtual ~DAC()
Definition NAFE33352.cpp:38
NAFE33352_Base::DAC::configure
void configure(const uint16_t(&cc)[6])
Definition NAFE33352.cpp:48
NAFE33352_Base::DAC::ModeSelect
ModeSelect
Definition NAFE33352.h:99
NAFE33352_Base::DAC::ModeSelect::DAC_OFF_CURRENT_IN
@ DAC_OFF_CURRENT_IN
Definition NAFE33352.h:105
NAFE33352_Base::DAC::ModeSelect::OFF
@ OFF
Definition NAFE33352.h:100
NAFE33352_Base::DAC::ModeSelect::CURRENT
@ CURRENT
Definition NAFE33352.h:102
NAFE33352_Base::DAC::ModeSelect::CURRENT_RECAL
@ CURRENT_RECAL
Definition NAFE33352.h:103
NAFE33352_Base::DAC::ModeSelect::DAC_OFF_VOLTAGE_IN
@ DAC_OFF_VOLTAGE_IN
Definition NAFE33352.h:104
NAFE33352_Base::DAC::ModeSelect::VOLTAGE
@ VOLTAGE
Definition NAFE33352.h:101
NAFE33352_Base::LogicalChannel
Definition NAFE33352.h:70
NAFE33352_Base::LogicalChannel::configure
void configure(const uint16_t(&cc)[3])
Definition NAFE33352.cpp:22
NAFE33352_Base::LogicalChannel::LogicalChannel
LogicalChannel()
Definition NAFE33352.cpp:13
NAFE33352_Base::LogicalChannel::~LogicalChannel
virtual ~LogicalChannel()
Definition NAFE33352.cpp:17
NAFE33352_Base::bit_op
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
Definition NAFE33352.h:472
NAFE33352_Base::on_board_shunt_resister
static constexpr double on_board_shunt_resister
Definition NAFE33352.h:20
NAFE33352_Base::part_number
uint64_t part_number(void)
Definition NAFE33352.cpp:473
NAFE33352_Base::revision_number
uint8_t revision_number(void)
Definition NAFE33352.cpp:478
NAFE33352_Base::read
virtual raw_t read(int ch)
Definition NAFE33352.cpp:411
NAFE33352_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition NAFE33352.cpp:368
NAFE33352_Base::Register16
Register16
Definition NAFE33352.h:289
NAFE33352_Base::Register16::AIO_STATUS
@ AIO_STATUS
Definition NAFE33352.h:327
NAFE33352_Base::Register16::AIO_PROT_CFG
@ AIO_PROT_CFG
Definition NAFE33352.h:323
NAFE33352_Base::Register16::CK_SRC_SEL_CONFIG
@ CK_SRC_SEL_CONFIG
Definition NAFE33352.h:303
NAFE33352_Base::Register16::AI_STATUS_OVR
@ AI_STATUS_OVR
Definition NAFE33352.h:318
NAFE33352_Base::Register16::GLOBAL_ALARM_INT
@ GLOBAL_ALARM_INT
Definition NAFE33352.h:305
NAFE33352_Base::Register16::SYS_CONFIG
@ SYS_CONFIG
Definition NAFE33352.h:301
NAFE33352_Base::Register16::CRC_TRIM_REGS
@ CRC_TRIM_REGS
Definition NAFE33352.h:292
NAFE33352_Base::Register16::PN1
@ PN1
Definition NAFE33352.h:309
NAFE33352_Base::Register16::CRC_COEF_REGS
@ CRC_COEF_REGS
Definition NAFE33352.h:291
NAFE33352_Base::Register16::GPI_EDGE_POS
@ GPI_EDGE_POS
Definition NAFE33352.h:298
NAFE33352_Base::Register16::AO_SLR_CTRL
@ AO_SLR_CTRL
Definition NAFE33352.h:324
NAFE33352_Base::Register16::GPIO_FUNCTION
@ GPIO_FUNCTION
Definition NAFE33352.h:296
NAFE33352_Base::Register16::AI_CONFIG2
@ AI_CONFIG2
Definition NAFE33352.h:314
NAFE33352_Base::Register16::AWG_PER
@ AWG_PER
Definition NAFE33352.h:325
NAFE33352_Base::Register16::PN0_REV
@ PN0_REV
Definition NAFE33352.h:310
NAFE33352_Base::Register16::AO_CAL_COEF
@ AO_CAL_COEF
Definition NAFE33352.h:322
NAFE33352_Base::Register16::AI_CONFIG0
@ AI_CONFIG0
Definition NAFE33352.h:312
NAFE33352_Base::Register16::GPI_DATA
@ GPI_DATA
Definition NAFE33352.h:294
NAFE33352_Base::Register16::SYS_STATUS
@ SYS_STATUS
Definition NAFE33352.h:302
NAFE33352_Base::Register16::GLOBAL_ALARM_ENABLE
@ GLOBAL_ALARM_ENABLE
Definition NAFE33352.h:304
NAFE33352_Base::Register16::AI_CONFIG1
@ AI_CONFIG1
Definition NAFE33352.h:313
NAFE33352_Base::Register16::DIE_TEMP
@ DIE_TEMP
Definition NAFE33352.h:306
NAFE33352_Base::Register16::GPI_ENABLE
@ GPI_ENABLE
Definition NAFE33352.h:297
NAFE33352_Base::Register16::TEMP_THRS
@ TEMP_THRS
Definition NAFE33352.h:307
NAFE33352_Base::Register16::GPO_ENABLE
@ GPO_ENABLE
Definition NAFE33352.h:295
NAFE33352_Base::Register16::CRC_CONF_REGS
@ CRC_CONF_REGS
Definition NAFE33352.h:290
NAFE33352_Base::Register16::GPO_DATA
@ GPO_DATA
Definition NAFE33352.h:300
NAFE33352_Base::Register16::CRC_TRIM_REF
@ CRC_TRIM_REF
Definition NAFE33352.h:293
NAFE33352_Base::Register16::AI_STATUS_UDR
@ AI_STATUS_UDR
Definition NAFE33352.h:319
NAFE33352_Base::Register16::GPI_EDGE_NEG
@ GPI_EDGE_NEG
Definition NAFE33352.h:299
NAFE33352_Base::Register16::AI_SYSCFG
@ AI_SYSCFG
Definition NAFE33352.h:316
NAFE33352_Base::Register16::PN2
@ PN2
Definition NAFE33352.h:308
NAFE33352_Base::Register16::AO_SYSCFG
@ AO_SYSCFG
Definition NAFE33352.h:326
NAFE33352_Base::Register16::AIO_CONFIG
@ AIO_CONFIG
Definition NAFE33352.h:321
NAFE33352_Base::Register16::AI_STATUS
@ AI_STATUS
Definition NAFE33352.h:317
NAFE33352_Base::Register16::AI_MULTI_CH_EN
@ AI_MULTI_CH_EN
Definition NAFE33352.h:315
NAFE33352_Base::Command
Command
Definition NAFE33352.h:390
NAFE33352_Base::CMD_WGEN_STOP
@ CMD_WGEN_STOP
Definition NAFE33352.h:417
NAFE33352_Base::CMD_CALC_CRC_FAC
@ CMD_CALC_CRC_FAC
Definition NAFE33352.h:397
NAFE33352_Base::CMD_CALC_CRC_CONFIG
@ CMD_CALC_CRC_CONFIG
Definition NAFE33352.h:395
NAFE33352_Base::CMD_CH7
@ CMD_CH7
Definition NAFE33352.h:406
NAFE33352_Base::CMD_CALC_CRC_COEF
@ CMD_CALC_CRC_COEF
Definition NAFE33352.h:396
NAFE33352_Base::CMD_CH0
@ CMD_CH0
Definition NAFE33352.h:399
NAFE33352_Base::CMD_AO_ABORT_HIZ
@ CMD_AO_ABORT_HIZ
Definition NAFE33352.h:421
NAFE33352_Base::CMD_END
@ CMD_END
Definition NAFE33352.h:408
NAFE33352_Base::CMD_MC
@ CMD_MC
Definition NAFE33352.h:413
NAFE33352_Base::CMD_SC
@ CMD_SC
Definition NAFE33352.h:411
NAFE33352_Base::CMD_MS
@ CMD_MS
Definition NAFE33352.h:414
NAFE33352_Base::CMD_RELOAD
@ CMD_RELOAD
Definition NAFE33352.h:394
NAFE33352_Base::CMD_AO_ABORT
@ CMD_AO_ABORT
Definition NAFE33352.h:420
NAFE33352_Base::CMD_CH1
@ CMD_CH1
Definition NAFE33352.h:400
NAFE33352_Base::CMD_ADC_ABORT
@ CMD_ADC_ABORT
Definition NAFE33352.h:407
NAFE33352_Base::CMD_WGEN_START
@ CMD_WGEN_START
Definition NAFE33352.h:418
NAFE33352_Base::CMD_CLEAR_DAC0
@ CMD_CLEAR_DAC0
Definition NAFE33352.h:419
NAFE33352_Base::CMD_CLEAR_ALARM
@ CMD_CLEAR_ALARM
Definition NAFE33352.h:391
NAFE33352_Base::CMD_CH4
@ CMD_CH4
Definition NAFE33352.h:403
NAFE33352_Base::CMD_SS
@ CMD_SS
Definition NAFE33352.h:410
NAFE33352_Base::CMD_CH3
@ CMD_CH3
Definition NAFE33352.h:402
NAFE33352_Base::CMD_CLEAR_REG
@ CMD_CLEAR_REG
Definition NAFE33352.h:393
NAFE33352_Base::CMD_CLEAR_DATA
@ CMD_CLEAR_DATA
Definition NAFE33352.h:409
NAFE33352_Base::CMD_RESET
@ CMD_RESET
Definition NAFE33352.h:392
NAFE33352_Base::CMD_BURST_DATA
@ CMD_BURST_DATA
Definition NAFE33352.h:415
NAFE33352_Base::CMD_CH6
@ CMD_CH6
Definition NAFE33352.h:405
NAFE33352_Base::CMD_MM
@ CMD_MM
Definition NAFE33352.h:412
NAFE33352_Base::CMD_CH5
@ CMD_CH5
Definition NAFE33352.h:404
NAFE33352_Base::CMD_CISW_ABORT_HIZ
@ CMD_CISW_ABORT_HIZ
Definition NAFE33352.h:423
NAFE33352_Base::CMD_CH2
@ CMD_CH2
Definition NAFE33352.h:401
NAFE33352_Base::CMD_CISW_ABORT
@ CMD_CISW_ABORT
Definition NAFE33352.h:422
NAFE33352_Base::boot
virtual void boot(void)
Definition NAFE33352.cpp:150
NAFE33352_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t dummy)
Definition NAFE33352.cpp:361
NAFE33352_Base::write_r24
virtual void write_r24(uint16_t reg, uint32_t val)
Definition NAFE33352.cpp:140
NAFE33352_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition NAFE33352.cpp:384
NAFE33352_Base::pga_gain
static constexpr double pga_gain[]
Definition NAFE33352.h:260
NAFE33352_Base::open_dac_output
void open_dac_output(const uint16_t(&cc)[6])
Definition NAFE33352.cpp:190
NAFE33352_Base::Register24
Register24
Definition NAFE33352.h:330
NAFE33352_Base::Register24::AI_CH_UDR_THR_5
@ AI_CH_UDR_THR_5
Definition NAFE33352.h:379
NAFE33352_Base::Register24::AWG_AMP_MIN
@ AWG_AMP_MIN
Definition NAFE33352.h:387
NAFE33352_Base::Register24::AI_CH_UDR_THR_4
@ AI_CH_UDR_THR_4
Definition NAFE33352.h:378
NAFE33352_Base::Register24::AI_DATA3
@ AI_DATA3
Definition NAFE33352.h:361
NAFE33352_Base::Register24::GAIN_COEF0
@ GAIN_COEF0
Definition NAFE33352.h:331
NAFE33352_Base::Register24::AO_OC_NEG_LIMIT
@ AO_OC_NEG_LIMIT
Definition NAFE33352.h:385
NAFE33352_Base::Register24::OFFSET_COEF3
@ OFFSET_COEF3
Definition NAFE33352.h:342
NAFE33352_Base::Register24::GAIN_COEF5
@ GAIN_COEF5
Definition NAFE33352.h:336
NAFE33352_Base::Register24::GAIN_COEF4
@ GAIN_COEF4
Definition NAFE33352.h:335
NAFE33352_Base::Register24::OFFSET_COEF2
@ OFFSET_COEF2
Definition NAFE33352.h:341
NAFE33352_Base::Register24::EXTRA_CAL_COEF4
@ EXTRA_CAL_COEF4
Definition NAFE33352.h:351
NAFE33352_Base::Register24::AI_CH_UDR_THR_7
@ AI_CH_UDR_THR_7
Definition NAFE33352.h:381
NAFE33352_Base::Register24::EXTRA_CAL_COEF2
@ EXTRA_CAL_COEF2
Definition NAFE33352.h:349
NAFE33352_Base::Register24::AI_CH_UDR_THR_0
@ AI_CH_UDR_THR_0
Definition NAFE33352.h:374
NAFE33352_Base::Register24::AI_CH_OVR_THR_6
@ AI_CH_OVR_THR_6
Definition NAFE33352.h:372
NAFE33352_Base::Register24::AI_CH_UDR_THR_6
@ AI_CH_UDR_THR_6
Definition NAFE33352.h:380
NAFE33352_Base::Register24::AI_DATA5
@ AI_DATA5
Definition NAFE33352.h:363
NAFE33352_Base::Register24::OFFSET_COEF5
@ OFFSET_COEF5
Definition NAFE33352.h:344
NAFE33352_Base::Register24::EXTRA_CAL_COEF1
@ EXTRA_CAL_COEF1
Definition NAFE33352.h:348
NAFE33352_Base::Register24::AI_CH_OVR_THR_3
@ AI_CH_OVR_THR_3
Definition NAFE33352.h:369
NAFE33352_Base::Register24::EXTRA_CAL_COEF5
@ EXTRA_CAL_COEF5
Definition NAFE33352.h:352
NAFE33352_Base::Register24::AI_DATA6
@ AI_DATA6
Definition NAFE33352.h:364
NAFE33352_Base::Register24::OFFSET_COEF4
@ OFFSET_COEF4
Definition NAFE33352.h:343
NAFE33352_Base::Register24::AI_DATA1
@ AI_DATA1
Definition NAFE33352.h:359
NAFE33352_Base::Register24::AI_DATA0
@ AI_DATA0
Definition NAFE33352.h:358
NAFE33352_Base::Register24::GAIN_COEF6
@ GAIN_COEF6
Definition NAFE33352.h:337
NAFE33352_Base::Register24::AI_CH_UDR_THR_3
@ AI_CH_UDR_THR_3
Definition NAFE33352.h:377
NAFE33352_Base::Register24::EXTRA_CAL_COEF7
@ EXTRA_CAL_COEF7
Definition NAFE33352.h:354
NAFE33352_Base::Register24::AI_CH_OVR_THR_0
@ AI_CH_OVR_THR_0
Definition NAFE33352.h:366
NAFE33352_Base::Register24::OFFSET_COEF6
@ OFFSET_COEF6
Definition NAFE33352.h:345
NAFE33352_Base::Register24::AI_CH_OVR_THR_1
@ AI_CH_OVR_THR_1
Definition NAFE33352.h:367
NAFE33352_Base::Register24::AI_DATA4
@ AI_DATA4
Definition NAFE33352.h:362
NAFE33352_Base::Register24::GAIN_COEF7
@ GAIN_COEF7
Definition NAFE33352.h:338
NAFE33352_Base::Register24::AO_DATA
@ AO_DATA
Definition NAFE33352.h:383
NAFE33352_Base::Register24::AI_CH_OVR_THR_5
@ AI_CH_OVR_THR_5
Definition NAFE33352.h:371
NAFE33352_Base::Register24::GAIN_COEF1
@ GAIN_COEF1
Definition NAFE33352.h:332
NAFE33352_Base::Register24::OFFSET_COEF0
@ OFFSET_COEF0
Definition NAFE33352.h:339
NAFE33352_Base::Register24::AO_OC_POS_LIMIT
@ AO_OC_POS_LIMIT
Definition NAFE33352.h:384
NAFE33352_Base::Register24::AI_CH_UDR_THR_1
@ AI_CH_UDR_THR_1
Definition NAFE33352.h:375
NAFE33352_Base::Register24::AWG_AMP_MAX
@ AWG_AMP_MAX
Definition NAFE33352.h:386
NAFE33352_Base::Register24::OFFSET_COEF1
@ OFFSET_COEF1
Definition NAFE33352.h:340
NAFE33352_Base::Register24::EXTRA_CAL_COEF6
@ EXTRA_CAL_COEF6
Definition NAFE33352.h:353
NAFE33352_Base::Register24::EXTRA_CAL_COEF0
@ EXTRA_CAL_COEF0
Definition NAFE33352.h:347
NAFE33352_Base::Register24::EXTRA_CAL_COEF3
@ EXTRA_CAL_COEF3
Definition NAFE33352.h:350
NAFE33352_Base::Register24::AI_CH_OVR_THR_4
@ AI_CH_OVR_THR_4
Definition NAFE33352.h:370
NAFE33352_Base::Register24::SERIAL0
@ SERIAL0
Definition NAFE33352.h:356
NAFE33352_Base::Register24::OFFSET_COEF7
@ OFFSET_COEF7
Definition NAFE33352.h:346
NAFE33352_Base::Register24::GAIN_COEF2
@ GAIN_COEF2
Definition NAFE33352.h:333
NAFE33352_Base::Register24::AI_CH_OVR_THR_7
@ AI_CH_OVR_THR_7
Definition NAFE33352.h:373
NAFE33352_Base::Register24::AI_CH_UDR_THR_2
@ AI_CH_UDR_THR_2
Definition NAFE33352.h:376
NAFE33352_Base::Register24::AI_DATA7
@ AI_DATA7
Definition NAFE33352.h:365
NAFE33352_Base::Register24::AI_CH_OVR_THR_2
@ AI_CH_OVR_THR_2
Definition NAFE33352.h:368
NAFE33352_Base::Register24::SERIAL1
@ SERIAL1
Definition NAFE33352.h:355
NAFE33352_Base::Register24::GAIN_COEF3
@ GAIN_COEF3
Definition NAFE33352.h:334
NAFE33352_Base::Register24::AI_DATA2
@ AI_DATA2
Definition NAFE33352.h:360
NAFE33352_Base::reset
virtual void reset(bool hardware_reset=false)
Definition NAFE33352.cpp:166
NAFE33352_Base::command
virtual void command(uint16_t com)
Definition NAFE33352.cpp:448
NAFE33352_Base::start
virtual void start(void)
Definition NAFE33352.cpp:396
NAFE33352_Base::GainPGA
GainPGA
Definition NAFE33352.h:284
NAFE33352_Base::G_PGA_x_1_0
@ G_PGA_x_1_0
Definition NAFE33352.h:285
NAFE33352_Base::G_PGA_x16_0
@ G_PGA_x16_0
Definition NAFE33352.h:286
NAFE33352_Base::~NAFE33352_Base
virtual ~NAFE33352_Base()
Definition NAFE33352.cpp:127
NAFE33352_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition NAFE33352.cpp:279
NAFE33352_Base::serial_number
uint64_t serial_number(void)
Definition NAFE33352.cpp:483
NAFE33352_Base::dac
DAC dac
Definition NAFE33352.h:160
NAFE33352_Base::dac_code
int32_t dac_code(double a, double full_scale, uint8_t bit_length)
Definition NAFE33352.cpp:436
NAFE33352_Base::NAFE33352_Base
NAFE33352_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition NAFE33352.cpp:115
NAFE33352_Base::calc_delay
double calc_delay(int ch)
Definition NAFE33352.cpp:304
NAFE33352_Base::start_continuous_conversion
virtual void start_continuous_conversion()
Definition NAFE33352.cpp:401
NAFE33352_Base::raw2v
double raw2v(int ch, raw_t value)
Definition NAFE33352.h:233
NAFE33352_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition NAFE33352.h:19
NAFE33352_Base::dac_out
virtual void dac_out(double vi, double full_scale, uint8_t bit_length)
Definition NAFE33352.cpp:431
NAFE33352_Base::IN_SEL
IN_SEL
Definition NAFE33352.h:262
NAFE33352_Base::VCM__REF_BYP
@ VCM__REF_BYP
Definition NAFE33352.h:275
NAFE33352_Base::AIP_VSNS
@ AIP_VSNS
Definition NAFE33352.h:265
NAFE33352_Base::DAC_REF
@ DAC_REF
Definition NAFE33352.h:281
NAFE33352_Base::AIP_AIN
@ AIP_AIN
Definition NAFE33352.h:264
NAFE33352_Base::REF_BYP__VCM
@ REF_BYP__VCM
Definition NAFE33352.h:274
NAFE33352_Base::VHSS
@ VHSS
Definition NAFE33352.h:280
NAFE33352_Base::LDO
@ LDO
Definition NAFE33352.h:278
NAFE33352_Base::BG
@ BG
Definition NAFE33352.h:276
NAFE33352_Base::VCM_VCM
@ VCM_VCM
Definition NAFE33352.h:263
NAFE33352_Base::AIN
@ AIN
Definition NAFE33352.h:268
NAFE33352_Base::VCM_GPIO1
@ VCM_GPIO1
Definition NAFE33352.h:273
NAFE33352_Base::VADD
@ VADD
Definition NAFE33352.h:277
NAFE33352_Base::AIP
@ AIP
Definition NAFE33352.h:267
NAFE33352_Base::VHDD
@ VHDD
Definition NAFE33352.h:279
NAFE33352_Base::GPIO0_GPIO1
@ GPIO0_GPIO1
Definition NAFE33352.h:266
NAFE33352_Base::GPIO0_VCM
@ GPIO0_VCM
Definition NAFE33352.h:272
NAFE33352_Base::ISNS
@ ISNS
Definition NAFE33352.h:269
NAFE33352_Base::TIA
@ TIA
Definition NAFE33352.h:271
NAFE33352_Base::VSNS
@ VSNS
Definition NAFE33352.h:270
NAFE33352_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition NAFE33352.cpp:406
NAFE33352_Base::txrx
virtual void txrx(uint8_t *data, int size, int cs_delay=0)
Definition NAFE33352.cpp:131
NAFE33352_Base::temperature
float temperature(void)
Definition NAFE33352.cpp:492
NAFE33352_Base::logical_channel
LogicalChannel logical_channel[16]
Definition NAFE33352.h:91
NAFE33352_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition NAFE33352.cpp:453
NAFE33352_UIOM::~NAFE33352_UIOM
virtual ~NAFE33352_UIOM()
Definition NAFE33352.cpp:515
NAFE33352_UIOM::NAFE33352_UIOM
NAFE33352_UIOM(bool spi_addr=0, bool highspeed_variant=false, int nINT=7, int DRDY=4, int SYN=14, int nRESET=14, int DRDY_input=2, int SYNCDAC=14)
Definition NAFE33352.cpp:510
NAFE33352::NAFE33352
NAFE33352(bool spi_addr=0, bool highspeed_variant=false, int nINT=7, int DRDY=4, int SYN=14, int nRESET=14, int DRDY_input=2, int SYNCDAC=14)
Definition NAFE33352.cpp:499
NAFE33352::~NAFE33352
virtual ~NAFE33352()
Definition NAFE33352.cpp:504