AFE_NXP_Arduino 2.0.5 Analog Front-End (AFE) device operation sample code for Arduino

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AFE_NXP.h
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1
9#ifndef ARDUINO_AFE_DRIVER_H
10#define ARDUINO_AFE_DRIVER_H
11
12#include <Arduino.h>
13#include <math.h>
14#include <stdint.h>
15#include <SPI_for_AFE.h>
16
17 class AFE_base : public SPI_for_AFE
18{
19 public:
20
22 using raw_t = int32_t;
23 using volt_t = double;
24
26 AFE_base( bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC );
27
29 virtual ~AFE_base();
30
37 virtual void begin( void );
38
40 virtual void boot( void ) = 0;
41
43 virtual void reset( bool hardware_reset = false ) = 0;
44
46 typedef void (*callback_fp_t)( void );
47
52 virtual void set_DRDY_callback( callback_fp_t fnc );
53
62 virtual void open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 ) = 0;
63
69 virtual void open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] ) = 0;
70
75 virtual void close_logical_channel( int ch ) = 0;
76
79 virtual void close_logical_channel( void ) = 0;
80
85 virtual void enable_logical_channel( int ch ) = 0;
86
91 virtual void start( int ch ) = 0;
92
95 virtual void start( void ) = 0;
96
99 virtual void start_continuous_conversion( void ) = 0;
100
105 virtual void DRDY_by_sequencer_done( bool flag = true ) = 0;
106
111 virtual raw_t read( int ch ) = 0;
112
117 virtual void read( raw_t *data_ptr ) = 0;
118
123 virtual void read( volt_t *data_ptr ) = 0;
124
129 virtual raw_t start_and_read( int ch );
130
131#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
132
137 virtual void start_and_read( raw_t *data_ptr );
138
139#else
144 template<typename T>
145 inline void start_and_read( T data )
146 {
147 double wait_time = cbf_DRDY ? -1.0 : total_delay * delay_accuracy;
148
149 start();
150 wait_conversion_complete( wait_time );
151
152 read( data );
153 };
154#endif
155
157 enum LV_mux_sel : uint8_t {
158 REF2_REF2 = 0,
159 GPIO0_GPIO1,
160 REFCOARSE_REF2,
161 VADD_REF2,
162 VHDD_REF2,
163 REF2_VHSS,
164 HV_MUX,
165 };
166
172 inline double raw2uv( int ch, raw_t value )
173 {
174 return raw2v( ch, value ) * 1e6;
175 }
176
182 inline double raw2mv( int ch, raw_t value )
183 {
184 return raw2v( ch, value ) * 1e3;
185 }
186
192 virtual double raw2v( int ch, raw_t value ) = 0;
193
198 inline double drdy_delay( int ch )
199 {
200 return ch_delay[ ch ];
201 }
202
205 inline double drdy_delay( void )
206 {
207 return total_delay;
208 }
209
211 inline int enabled_logical_channels( void )
212 {
213 return enabled_channels;
214 }
215
220 void use_DRDY_trigger( bool use = true );
221
222 protected:
223 bool dev_add;
224 bool highspeed_variant;
225 int pin_nINT;
226 int pin_DRDY;
227 int pin_SYN;
228 int pin_nRESET;
229 int pin_DRDY_input;
230 int pin_SYNCDAC;
231
232
238 int bit_count( uint32_t value );
239
241 int enabled_channels;
242
244 uint8_t sequence_order[ 16 ];
245
247 double coeff_V[ 16 ];
248
250 int mux_setting[ 16 ];
251
253 double ch_delay[ 16 ];
254 double total_delay;
255 static double delay_accuracy;
256
257 constexpr static uint32_t timeout_limit = 10000000;
258
259 void default_drdy_cb();
260 static void static_default_drdy_cb();
261 uint32_t drdy_count;
262 volatile bool drdy_flag;
263 static callback_fp_t cbf_DRDY;
264 static void DRDY_cb();
265
267 virtual void init( void );
268
274 int wait_conversion_complete( double delay = -1.0 );
275
276 public:
277 static AFE_base* instance;
278};
279
280 class LogicalChannel_Base
281{
282 public:
283 LogicalChannel_Base() {}
284 virtual ~LogicalChannel_Base() {}
285
287 void enable( void );
289 void disable( void );
290
295 template<class T> T read(void);
296
298 operator AFE_base::raw_t(void);
300 operator AFE_base::volt_t(void);
301
303 template<class T> double operator+( T v ) { return (double)(*this) + (double)v; }
304 template<class T> double operator-( T v ) { return (double)(*this) - (double)v; }
305 template<class T> double operator*( T v ) { return (double)(*this) * (double)v; }
306 template<class T> double operator/( T v ) { return (double)(*this) / (double)v; }
307 template<class T> friend double operator+( T v, LogicalChannel_Base lc ) { return (double)v + (double)lc; }
308 template<class T> friend double operator-( T v, LogicalChannel_Base lc ) { return (double)v - (double)lc; }
309 template<class T> friend double operator*( T v, LogicalChannel_Base lc ) { return (double)v * (double)lc; }
310 template<class T> friend double operator/( T v, LogicalChannel_Base lc ) { return (double)v / (double)lc; }
313 int ch_number;
314 AFE_base *afe_ptr;
315};
316
317 class NAFE13388_Base : public AFE_base
318{
319 public:
320 using ch_setting_t = uint16_t[ 4 ];
321
322 typedef struct _reference_point {
323 double voltage;
324 int32_t data;
325 } reference_point;
326
327 typedef struct _ref_points {
328 int coeff_index;
329 reference_point high;
330 reference_point low;
331 int cal_index;
332 } ref_points;
333
335 NAFE13388_Base( bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC );
336
338 virtual ~NAFE13388_Base();
339
341 virtual void boot( void );
342
344 virtual void reset( bool hardware_reset = false );
345
354 virtual void open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 );
355
361 virtual void open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] );
362
363 class LogicalChannel : public LogicalChannel_Base
364 {
365 public:
366 LogicalChannel();
367 virtual ~LogicalChannel();
368
373 void configure( const uint16_t (&cc)[ 4 ] );
374
382 void configure( uint16_t cc0 = 0x0000, uint16_t cc1 = 0x0000, uint16_t cc2 = 0x0000, uint16_t cc3 = 0x0000 );
383 };
384
385 LogicalChannel logical_channel[ 16 ];
386
387 private:
388 double calc_delay( int ch );
389 void channel_info_update( uint16_t value );
390
391 public:
396 virtual void close_logical_channel( int ch );
397
400 virtual void close_logical_channel( void );
401
406 void enable_logical_channel( int ch );
407
412 virtual void start( int ch );
413
416 virtual void start( void );
417
420 virtual void start_continuous_conversion();
421
426 virtual void DRDY_by_sequencer_done( bool flag = true );
427
432 virtual raw_t read( int ch );
433
438 virtual void read( raw_t *data );
439
444 virtual void read( volt_t *data );
445
451 inline double raw2v( int ch, raw_t value )
452 {
453 double v = value * coeff_V[ ch ];
454
455 if ( HV_MUX != mux_setting[ ch ] )
456 {
457 switch ( mux_setting[ ch ] )
458 {
459 case REF2_REF2:
460 case GPIO0_GPIO1:
461 return v;
462 break;
463 case REFCOARSE_REF2:
464 case VADD_REF2:
465 return 2.00 * (v + 1.50);
466 break;
467 case VHDD_REF2:
468 return 32.00 * (v + 0.25);
469 break;
470 case REF2_VHSS:
471 return -32.00 * (v - 0.25);
472 break;
473 }
474 }
475 return v;
476 }
477
478
479// constexpr static double pga_gain[] = { 0.2, 0.4, 0.8, 1, 2, 4, 8, 16 };
480 static double pga_gain[];
481
482 enum GainPGA : uint8_t {
483 G_PGA_x_0_2 = 0,
484 G_PGA_x_0_4,
485 G_PGA_x_0_8,
486 G_PGA_x_1_0,
487 G_PGA_x_2_0,
488 G_PGA_x_4_0,
489 G_PGA_x_8_0,
490 G_PGA_x16_0,
491 };
492
493 enum class Register16 : uint16_t {
494 CH_CONFIG0 = 0x20,
495 CH_CONFIG1 = 0x21,
496 CH_CONFIG2 = 0x22,
497 CH_CONFIG3 = 0x23,
498 CH_CONFIG4 = 0x24,
499 CRC_CONF_REGS = 0x25,
500 CRC_COEF_REGS = 0x26,
501 CRC_TRIM_REGS = 0x27,
502 GPI_DATA = 0x29,
503 GPIO_CONFIG0 = 0x2A,
504 GPIO_CONFIG1 = 0x2B,
505 GPIO_CONFIG2 = 0x2C,
506 GPI_EDGE_POS = 0x2D,
507 GPI_EDGE_NEG = 0x2E,
508 GPO_DATA = 0x2F,
509 SYS_CONFIG0 = 0x30,
510 SYS_STATUS0 = 0x31,
511 GLOBAL_ALARM_ENABLE = 0x32,
512 GLOBAL_ALARM_INTERRUPT = 0x33,
513 DIE_TEMP = 0x34,
514 CH_STATUS0 = 0x35,
515 CH_STATUS1 = 0x36,
516 THRS_TEMP = 0x37,
517 PN2 = 0x7C,
518 PN1 = 0x7D,
519 PN0 = 0x7E,
520 CRC_TRIM_INT = 0x7F,
521 };
522
523 enum class Register24 : uint16_t {
524 CH_DATA0 = 0x40,
525 CH_DATA1 = 0x41,
526 CH_DATA2 = 0x42,
527 CH_DATA3 = 0x43,
528 CH_DATA4 = 0x44,
529 CH_DATA5 = 0x45,
530 CH_DATA6 = 0x46,
531 CH_DATA7 = 0x47,
532 CH_DATA8 = 0x48,
533 CH_DATA9 = 0x4A,
534 CH_DATA10 = 0x4B,
535 CH_DATA11 = 0x4C,
536 CH_DATA13 = 0x4D,
537 CH_DATA14 = 0x4E,
538 CH_DATA15 = 0x4F,
539 CH_CONFIG5_0 = 0x50,
540 CH_CONFIG5_1 = 0x51,
541 CH_CONFIG5_2 = 0x52,
542 CH_CONFIG5_3 = 0x53,
543 CH_CONFIG5_4 = 0x54,
544 CH_CONFIG5_5 = 0x55,
545 CH_CONFIG5_6 = 0x56,
546 CH_CONFIG5_7 = 0x57,
547 CH_CONFIG5_8 = 0x58,
548 CH_CONFIG5_9 = 0x59,
549 CH_CONFIG5_10 = 0x5A,
550 CH_CONFIG5_11 = 0x5B,
551 CH_CONFIG5_12 = 0x5C,
552 CH_CONFIG5_13 = 0x5D,
553 CH_CONFIG5_14 = 0x5E,
554 CH_CONFIG5_15 = 0x5F,
555 CH_CONFIG6_0 = 0x60,
556 CH_CONFIG6_1 = 0x61,
557 CH_CONFIG6_2 = 0x62,
558 CH_CONFIG6_3 = 0x63,
559 CH_CONFIG6_4 = 0x64,
560 CH_CONFIG6_5 = 0x65,
561 CH_CONFIG6_6 = 0x66,
562 CH_CONFIG6_7 = 0x67,
563 CH_CONFIG6_8 = 0x68,
564 CH_CONFIG6_9 = 0x69,
565 CH_CONFIG6_10 = 0x6A,
566 CH_CONFIG6_11 = 0x6B,
567 CH_CONFIG6_12 = 0x6C,
568 CH_CONFIG6_13 = 0x6D,
569 CH_CONFIG6_14 = 0x6E,
570 CH_CONFIG6_15 = 0x6F,
571 GAIN_COEFF0 = 0x80,
572 GAIN_COEFF1 = 0x81,
573 GAIN_COEFF2 = 0x82,
574 GAIN_COEFF3 = 0x83,
575 GAIN_COEFF4 = 0x84,
576 GAIN_COEFF5 = 0x85,
577 GAIN_COEFF6 = 0x86,
578 GAIN_COEFF7 = 0x87,
579 GAIN_COEFF8 = 0x88,
580 GAIN_COEFF9 = 0x89,
581 GAIN_COEFF10 = 0x8A,
582 GAIN_COEFF11 = 0x8B,
583 GAIN_COEFF12 = 0x8C,
584 GAIN_COEFF13 = 0x8D,
585 GAIN_COEFF14 = 0x8E,
586 GAIN_COEFF15 = 0x8F,
587 OFFSET_COEFF0 = 0x90,
588 OFFSET_COEFF1 = 0x91,
589 OFFSET_COEFF2 = 0x92,
590 OFFSET_COEFF3 = 0x93,
591 OFFSET_COEFF4 = 0x94,
592 OFFSET_COEFF5 = 0x95,
593 OFFSET_COEFF6 = 0x96,
594 OFFSET_COEFF7 = 0x97,
595 OFFSET_COEFF8 = 0x98,
596 OFFSET_COEFF9 = 0x99,
597 OFFSET_COEFF10 = 0x9A,
598 OFFSET_COEFF11 = 0x9B,
599 OFFSET_COEFF12 = 0x9C,
600 OFFSET_COEFF13 = 0x9D,
601 OFFSET_COEFF14 = 0x9E,
602 OFFSET_COEFF15 = 0x9F,
603 OPT_COEF0 = 0xA0,
604 OPT_COEF1 = 0xA1,
605 OPT_COEF2 = 0xA2,
606 OPT_COEF3 = 0xA3,
607 OPT_COEF4 = 0xA4,
608 OPT_COEF5 = 0xA5,
609 OPT_COEF6 = 0xA6,
610 OPT_COEF7 = 0xA7,
611 OPT_COEF8 = 0xA8,
612 OPT_COEF9 = 0xA9,
613 OPT_COEF10 = 0xAA,
614 OPT_COEF11 = 0xAB,
615 OPT_COEF12 = 0xAC,
616 OPT_COEF13 = 0xAD,
617 SERIAL1 = 0xAE,
618 SERIAL0 = 0xAF,
619 };
620
621 enum Command : uint16_t {
622 CMD_CH0 = 0x0000,
623 CMD_CH1 = 0x0001,
624 CMD_CH2 = 0x0002,
625 CMD_CH3 = 0x0003,
626 CMD_CH4 = 0x0004,
627 CMD_CH5 = 0x0005,
628 CMD_CH6 = 0x0006,
629 CMD_CH7 = 0x0007,
630 CMD_CH8 = 0x0008,
631 CMD_CH9 = 0x0009,
632 CMD_CH10 = 0x000A,
633 CMD_CH11 = 0x000B,
634 CMD_CH12 = 0x000C,
635 CMD_CH13 = 0x000D,
636 CMD_CH14 = 0x000E,
637 CMD_CH15 = 0x000F,
638 CMD_ABORT = 0x0010,
639 CMD_END = 0x0011,
640 CMD_CLEAR_ALARM = 0x0012,
641 CMD_CLEAR_DATA = 0x0013,
642 CMD_RESET = 0x0014,
643 CMD_CLEAR_REG = 0x0015,
644 CMD_RELOAD = 0x0016,
645 TBD = 0x0017,
646 CMD_SS = 0x2000,
647 CMD_SC = 0x2001,
648 CMD_MM = 0x2002,
649 CMD_MC = 0x2003,
650 CMD_MS = 0x2004,
651 CMD_BURST_DATA = 0x2005,
652 CMD_CALC_CRC_CONFG = 0x2006,
653 CMD_CALC_CRC_COEF = 0x2007,
654 CMD_CALC_CRC_FAC = 0x2008,
655 };
656
661 virtual void command( uint16_t com );
662
669 virtual void reg( Register16 r, uint16_t value );
670
677 virtual void reg( Register24 r, uint32_t value );
678
685 virtual uint16_t reg( Register16 r );
686
693 virtual uint32_t reg( Register24 r );
694
702 template<typename T>
703 uint32_t bit_op( T rg, uint32_t mask, uint32_t value )
704 {
705 uint32_t v = reg( rg );
706
707 v &= mask;
708 v |= value & ~mask;
709
710 reg( rg, v );
711
712 return v;
713 }
714
719 uint32_t part_number( void );
720
725 uint8_t revision_number( void );
726
731 uint64_t serial_number( void );
732
737 float temperature( void );
738
744 void gain_offset_coeff( const ref_points &ref );
745
746 enum CalibrationError : int {
747 NoError = 0,
748 GainError = -1,
749 OffsetError = -2,
750 };
751
763 int self_calibrate( int pga_gain_index, int channel_selection = 15, int input_select = 0, double reference_source_voltage = 0, bool use_positive_side = true );
764
766 void blink_leds( void );
767};
768
769 class NAFE13388 : public NAFE13388_Base
770{
771 public:
773 NAFE13388( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 2, int DRDY = 4, int SYN = 5, int nRESET = 6, int DRDY_input = 15, int SYNCDAC = 14 );
774
776 virtual ~NAFE13388();
777};
778
779 class NAFE13388_UIM : public NAFE13388_Base
780{
781 public:
783 NAFE13388_UIM( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 3, int DRDY = 4, int SYN = 6, int nRESET = 7, int DRDY_input = 2, int SYNCDAC = 14 );
784
786 virtual ~NAFE13388_UIM();
787
789 void blink_leds( void );
790};
791
792 inline NAFE13388_Base::Register16 operator+( NAFE13388_Base::Register16 rn, int n )
793{
794 return static_cast<NAFE13388_Base::Register16>( static_cast<uint16_t>( rn ) + n );
795}
796
797 inline NAFE13388_Base::Register16 operator+( int n, NAFE13388_Base::Register16 rn )
798{
799 return static_cast<NAFE13388_Base::Register16>( n + static_cast<uint16_t>( rn ) );
800}
801
802 inline NAFE13388_Base::Register24 operator+( NAFE13388_Base::Register24 rn, int n )
803{
804 return static_cast<NAFE13388_Base::Register24>( static_cast<uint16_t>( rn ) + n );
805}
806
807 inline NAFE13388_Base::Register24 operator+( int n, NAFE13388_Base::Register24 rn )
808{
809 return static_cast<NAFE13388_Base::Register24>( n + static_cast<uint16_t>( rn ) );
810}
811
812#endif // ARDUINO_AFE_DRIVER_H
operator+
NAFE13388_Base::Register16 operator+(NAFE13388_Base::Register16 rn, int n)
Definition AFE_NXP.h:792
SPI_for_AFE.h
AFE_base
Definition AFE_NXP.h:18
AFE_base::enable_logical_channel
virtual void enable_logical_channel(int ch)=0
AFE_base::start_continuous_conversion
virtual void start_continuous_conversion(void)=0
AFE_base::instance
static AFE_base * instance
Definition AFE_NXP.h:277
AFE_base::cbf_DRDY
static callback_fp_t cbf_DRDY
Definition AFE_NXP.h:263
AFE_base::close_logical_channel
virtual void close_logical_channel(void)=0
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::volt_t
double volt_t
Definition AFE_NXP.h:23
AFE_base::use_DRDY_trigger
void use_DRDY_trigger(bool use=true)
Definition AFE_NXP.cpp:194
AFE_base::~AFE_base
virtual ~AFE_base()
Definition AFE_NXP.cpp:84
AFE_base::open_logical_channel
virtual void open_logical_channel(int ch, const uint16_t(&cc)[4])=0
AFE_base::DRDY_cb
static void DRDY_cb()
Definition AFE_NXP.cpp:114
AFE_base::raw2v
virtual double raw2v(int ch, raw_t value)=0
AFE_base::read
virtual void read(volt_t *data_ptr)=0
AFE_base::pin_nINT
int pin_nINT
Definition AFE_NXP.h:225
AFE_base::set_DRDY_callback
virtual void set_DRDY_callback(callback_fp_t fnc)
Definition AFE_NXP.cpp:109
AFE_base::pin_DRDY_input
int pin_DRDY_input
Definition AFE_NXP.h:229
AFE_base::init
virtual void init(void)
Definition AFE_NXP.cpp:88
AFE_base::timeout_limit
static constexpr uint32_t timeout_limit
Definition AFE_NXP.h:257
AFE_base::begin
virtual void begin(void)
Definition AFE_NXP.cpp:98
AFE_base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)=0
AFE_base::drdy_delay
double drdy_delay(int ch)
Definition AFE_NXP.h:198
AFE_base::raw2mv
double raw2mv(int ch, raw_t value)
Definition AFE_NXP.h:182
AFE_base::LV_mux_sel
LV_mux_sel
Definition AFE_NXP.h:157
AFE_base::VADD_REF2
@ VADD_REF2
Definition AFE_NXP.h:161
AFE_base::HV_MUX
@ HV_MUX
Definition AFE_NXP.h:164
AFE_base::REF2_VHSS
@ REF2_VHSS
Definition AFE_NXP.h:163
AFE_base::GPIO0_GPIO1
@ GPIO0_GPIO1
Definition AFE_NXP.h:159
AFE_base::REF2_REF2
@ REF2_REF2
Definition AFE_NXP.h:158
AFE_base::REFCOARSE_REF2
@ REFCOARSE_REF2
Definition AFE_NXP.h:160
AFE_base::VHDD_REF2
@ VHDD_REF2
Definition AFE_NXP.h:162
AFE_base::highspeed_variant
bool highspeed_variant
Definition AFE_NXP.h:224
AFE_base::enabled_logical_channels
int enabled_logical_channels(void)
Definition AFE_NXP.h:211
AFE_base::reset
virtual void reset(bool hardware_reset=false)=0
AFE_base::drdy_count
uint32_t drdy_count
Definition AFE_NXP.h:261
AFE_base::bit_count
int bit_count(uint32_t value)
Definition AFE_NXP.cpp:155
AFE_base::pin_SYNCDAC
int pin_SYNCDAC
Definition AFE_NXP.h:230
AFE_base::read
virtual void read(raw_t *data_ptr)=0
AFE_base::start
virtual void start(int ch)=0
AFE_base::default_drdy_cb
void default_drdy_cb()
Definition AFE_NXP.cpp:126
AFE_base::raw2uv
double raw2uv(int ch, raw_t value)
Definition AFE_NXP.h:172
AFE_base::callback_fp_t
void(* callback_fp_t)(void)
Definition AFE_NXP.h:46
AFE_base::coeff_V
double coeff_V[16]
Definition AFE_NXP.h:247
AFE_base::start_and_read
virtual raw_t start_and_read(int ch)
Definition AFE_NXP.cpp:132
AFE_base::enabled_channels
int enabled_channels
Definition AFE_NXP.h:241
AFE_base::sequence_order
uint8_t sequence_order[16]
Definition AFE_NXP.h:244
AFE_base::static_default_drdy_cb
static void static_default_drdy_cb()
Definition AFE_NXP.cpp:120
AFE_base::start
virtual void start(void)=0
AFE_base::wait_conversion_complete
int wait_conversion_complete(double delay=-1.0)
Definition AFE_NXP.cpp:168
AFE_base::close_logical_channel
virtual void close_logical_channel(int ch)=0
AFE_base::drdy_flag
volatile bool drdy_flag
Definition AFE_NXP.h:262
AFE_base::pin_SYN
int pin_SYN
Definition AFE_NXP.h:227
AFE_base::delay_accuracy
static double delay_accuracy
Definition AFE_NXP.h:255
AFE_base::ch_delay
double ch_delay[16]
Definition AFE_NXP.h:253
AFE_base::mux_setting
int mux_setting[16]
Definition AFE_NXP.h:250
AFE_base::boot
virtual void boot(void)=0
AFE_base::pin_nRESET
int pin_nRESET
Definition AFE_NXP.h:228
AFE_base::dev_add
bool dev_add
Definition AFE_NXP.h:223
AFE_base::start_and_read
void start_and_read(T data)
Definition AFE_NXP.h:145
AFE_base::drdy_delay
double drdy_delay(void)
Definition AFE_NXP.h:205
AFE_base::read
virtual raw_t read(int ch)=0
AFE_base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)=0
AFE_base::pin_DRDY
int pin_DRDY
Definition AFE_NXP.h:226
AFE_base::total_delay
double total_delay
Definition AFE_NXP.h:254
LogicalChannel_Base
Definition AFE_NXP.h:281
LogicalChannel_Base::~LogicalChannel_Base
virtual ~LogicalChannel_Base()
Definition AFE_NXP.h:284
LogicalChannel_Base::operator+
double operator+(T v)
Definition AFE_NXP.h:303
LogicalChannel_Base::operator-
friend double operator-(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:308
LogicalChannel_Base::read
T read(void)
LogicalChannel_Base::LogicalChannel_Base
LogicalChannel_Base()
Definition AFE_NXP.h:283
LogicalChannel_Base::enable
void enable(void)
Definition AFE_NXP.cpp:14
LogicalChannel_Base::afe_ptr
AFE_base * afe_ptr
Definition AFE_NXP.h:314
LogicalChannel_Base::operator-
double operator-(T v)
Definition AFE_NXP.h:304
LogicalChannel_Base::operator*
double operator*(T v)
Definition AFE_NXP.h:305
LogicalChannel_Base::operator/
friend double operator/(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:310
LogicalChannel_Base::operator*
friend double operator*(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:309
LogicalChannel_Base::operator+
friend double operator+(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:307
LogicalChannel_Base::operator/
double operator/(T v)
Definition AFE_NXP.h:306
LogicalChannel_Base::ch_number
int ch_number
Definition AFE_NXP.h:313
LogicalChannel_Base::disable
void disable(void)
Definition AFE_NXP.cpp:19
NAFE13388_Base::LogicalChannel
Definition AFE_NXP.h:364
NAFE13388_Base::LogicalChannel::~LogicalChannel
virtual ~LogicalChannel()
Definition AFE_NXP.cpp:51
NAFE13388_Base::LogicalChannel::LogicalChannel
LogicalChannel()
Definition AFE_NXP.cpp:47
NAFE13388_Base::LogicalChannel::configure
void configure(const uint16_t(&cc)[4])
Definition AFE_NXP.cpp:56
NAFE13388_Base
Definition AFE_NXP.h:318
NAFE13388_Base::start_continuous_conversion
virtual void start_continuous_conversion()
Definition AFE_NXP.cpp:396
NAFE13388_Base::raw2v
double raw2v(int ch, raw_t value)
Definition AFE_NXP.h:451
NAFE13388_Base::boot
virtual void boot(void)
Definition AFE_NXP.cpp:222
NAFE13388_Base::gain_offset_coeff
void gain_offset_coeff(const ref_points &ref)
Definition AFE_NXP.cpp:475
NAFE13388_Base::calc_delay
double calc_delay(int ch)
Definition AFE_NXP.cpp:307
NAFE13388_Base::command
virtual void command(uint16_t com)
Definition AFE_NXP.cpp:426
NAFE13388_Base::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:611
NAFE13388_Base::read
virtual raw_t read(int ch)
Definition AFE_NXP.cpp:406
NAFE13388_Base::logical_channel
LogicalChannel logical_channel[16]
Definition AFE_NXP.h:385
NAFE13388_Base::pga_gain
static double pga_gain[]
Definition AFE_NXP.h:670
NAFE13388_Base::bit_op
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
Definition AFE_NXP.h:703
NAFE13388_Base::self_calibrate
int self_calibrate(int pga_gain_index, int channel_selection=15, int input_select=0, double reference_source_voltage=0, bool use_positive_side=true)
Definition AFE_NXP.cpp:507
NAFE13388_Base::ref_points
struct NAFE13388_Base::_ref_points ref_points
NAFE13388_Base::start
virtual void start(void)
Definition AFE_NXP.cpp:391
NAFE13388_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition AFE_NXP.cpp:431
NAFE13388_Base::GainPGA
GainPGA
Definition AFE_NXP.h:482
NAFE13388_Base::G_PGA_x_0_8
@ G_PGA_x_0_8
Definition AFE_NXP.h:485
NAFE13388_Base::G_PGA_x_0_4
@ G_PGA_x_0_4
Definition AFE_NXP.h:484
NAFE13388_Base::G_PGA_x_4_0
@ G_PGA_x_4_0
Definition AFE_NXP.h:488
NAFE13388_Base::G_PGA_x16_0
@ G_PGA_x16_0
Definition AFE_NXP.h:490
NAFE13388_Base::G_PGA_x_8_0
@ G_PGA_x_8_0
Definition AFE_NXP.h:489
NAFE13388_Base::G_PGA_x_0_2
@ G_PGA_x_0_2
Definition AFE_NXP.h:483
NAFE13388_Base::G_PGA_x_1_0
@ G_PGA_x_1_0
Definition AFE_NXP.h:486
NAFE13388_Base::G_PGA_x_2_0
@ G_PGA_x_2_0
Definition AFE_NXP.h:487
NAFE13388_Base::reference_point
struct NAFE13388_Base::_reference_point reference_point
NAFE13388_Base::revision_number
uint8_t revision_number(void)
Definition AFE_NXP.cpp:456
NAFE13388_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition AFE_NXP.cpp:379
NAFE13388_Base::Register24
Register24
Definition AFE_NXP.h:523
NAFE13388_Base::Register24::OFFSET_COEFF10
@ OFFSET_COEFF10
NAFE13388_Base::Register24::CH_DATA2
@ CH_DATA2
NAFE13388_Base::Register24::CH_CONFIG5_7
@ CH_CONFIG5_7
NAFE13388_Base::Register24::CH_DATA3
@ CH_DATA3
NAFE13388_Base::Register24::OFFSET_COEFF3
@ OFFSET_COEFF3
NAFE13388_Base::Register24::CH_CONFIG5_2
@ CH_CONFIG5_2
NAFE13388_Base::Register24::CH_CONFIG6_14
@ CH_CONFIG6_14
NAFE13388_Base::Register24::CH_CONFIG5_5
@ CH_CONFIG5_5
NAFE13388_Base::Register24::GAIN_COEFF5
@ GAIN_COEFF5
NAFE13388_Base::Register24::CH_CONFIG6_11
@ CH_CONFIG6_11
NAFE13388_Base::Register24::CH_DATA9
@ CH_DATA9
NAFE13388_Base::Register24::OFFSET_COEFF0
@ OFFSET_COEFF0
NAFE13388_Base::Register24::CH_CONFIG5_4
@ CH_CONFIG5_4
NAFE13388_Base::Register24::CH_DATA15
@ CH_DATA15
NAFE13388_Base::Register24::OPT_COEF4
@ OPT_COEF4
NAFE13388_Base::Register24::GAIN_COEFF4
@ GAIN_COEFF4
NAFE13388_Base::Register24::CH_CONFIG6_10
@ CH_CONFIG6_10
NAFE13388_Base::Register24::OFFSET_COEFF15
@ OFFSET_COEFF15
NAFE13388_Base::Register24::OFFSET_COEFF8
@ OFFSET_COEFF8
NAFE13388_Base::Register24::OPT_COEF6
@ OPT_COEF6
NAFE13388_Base::Register24::OFFSET_COEFF11
@ OFFSET_COEFF11
NAFE13388_Base::Register24::CH_CONFIG5_10
@ CH_CONFIG5_10
NAFE13388_Base::Register24::CH_CONFIG6_5
@ CH_CONFIG6_5
NAFE13388_Base::Register24::CH_DATA5
@ CH_DATA5
NAFE13388_Base::Register24::CH_CONFIG5_1
@ CH_CONFIG5_1
NAFE13388_Base::Register24::GAIN_COEFF12
@ GAIN_COEFF12
NAFE13388_Base::Register24::GAIN_COEFF0
@ GAIN_COEFF0
NAFE13388_Base::Register24::CH_CONFIG6_3
@ CH_CONFIG6_3
NAFE13388_Base::Register24::GAIN_COEFF15
@ GAIN_COEFF15
NAFE13388_Base::Register24::CH_CONFIG6_8
@ CH_CONFIG6_8
NAFE13388_Base::Register24::CH_CONFIG5_15
@ CH_CONFIG5_15
NAFE13388_Base::Register24::CH_DATA13
@ CH_DATA13
NAFE13388_Base::Register24::GAIN_COEFF14
@ GAIN_COEFF14
NAFE13388_Base::Register24::CH_DATA4
@ CH_DATA4
NAFE13388_Base::Register24::OPT_COEF12
@ OPT_COEF12
NAFE13388_Base::Register24::OFFSET_COEFF5
@ OFFSET_COEFF5
NAFE13388_Base::Register24::OFFSET_COEFF4
@ OFFSET_COEFF4
NAFE13388_Base::Register24::CH_CONFIG6_13
@ CH_CONFIG6_13
NAFE13388_Base::Register24::OPT_COEF5
@ OPT_COEF5
NAFE13388_Base::Register24::OPT_COEF2
@ OPT_COEF2
NAFE13388_Base::Register24::CH_CONFIG5_6
@ CH_CONFIG5_6
NAFE13388_Base::Register24::CH_CONFIG6_7
@ CH_CONFIG6_7
NAFE13388_Base::Register24::GAIN_COEFF11
@ GAIN_COEFF11
NAFE13388_Base::Register24::CH_DATA8
@ CH_DATA8
NAFE13388_Base::Register24::CH_CONFIG5_9
@ CH_CONFIG5_9
NAFE13388_Base::Register24::GAIN_COEFF1
@ GAIN_COEFF1
NAFE13388_Base::Register24::OFFSET_COEFF7
@ OFFSET_COEFF7
NAFE13388_Base::Register24::CH_DATA6
@ CH_DATA6
NAFE13388_Base::Register24::GAIN_COEFF2
@ GAIN_COEFF2
NAFE13388_Base::Register24::GAIN_COEFF10
@ GAIN_COEFF10
NAFE13388_Base::Register24::GAIN_COEFF3
@ GAIN_COEFF3
NAFE13388_Base::Register24::GAIN_COEFF8
@ GAIN_COEFF8
NAFE13388_Base::Register24::OPT_COEF7
@ OPT_COEF7
NAFE13388_Base::Register24::CH_DATA10
@ CH_DATA10
NAFE13388_Base::Register24::CH_DATA7
@ CH_DATA7
NAFE13388_Base::Register24::OFFSET_COEFF9
@ OFFSET_COEFF9
NAFE13388_Base::Register24::CH_CONFIG6_2
@ CH_CONFIG6_2
NAFE13388_Base::Register24::OPT_COEF9
@ OPT_COEF9
NAFE13388_Base::Register24::CH_DATA11
@ CH_DATA11
NAFE13388_Base::Register24::CH_CONFIG5_11
@ CH_CONFIG5_11
NAFE13388_Base::Register24::GAIN_COEFF6
@ GAIN_COEFF6
NAFE13388_Base::Register24::CH_CONFIG6_12
@ CH_CONFIG6_12
NAFE13388_Base::Register24::OFFSET_COEFF6
@ OFFSET_COEFF6
NAFE13388_Base::Register24::GAIN_COEFF9
@ GAIN_COEFF9
NAFE13388_Base::Register24::CH_CONFIG5_3
@ CH_CONFIG5_3
NAFE13388_Base::Register24::CH_CONFIG5_8
@ CH_CONFIG5_8
NAFE13388_Base::Register24::CH_DATA14
@ CH_DATA14
NAFE13388_Base::Register24::SERIAL0
@ SERIAL0
NAFE13388_Base::Register24::CH_DATA1
@ CH_DATA1
NAFE13388_Base::Register24::OPT_COEF13
@ OPT_COEF13
NAFE13388_Base::Register24::CH_CONFIG6_9
@ CH_CONFIG6_9
NAFE13388_Base::Register24::OFFSET_COEFF1
@ OFFSET_COEFF1
NAFE13388_Base::Register24::CH_CONFIG6_4
@ CH_CONFIG6_4
NAFE13388_Base::Register24::OFFSET_COEFF13
@ OFFSET_COEFF13
NAFE13388_Base::Register24::OPT_COEF0
@ OPT_COEF0
NAFE13388_Base::Register24::CH_CONFIG5_0
@ CH_CONFIG5_0
NAFE13388_Base::Register24::OPT_COEF11
@ OPT_COEF11
NAFE13388_Base::Register24::GAIN_COEFF7
@ GAIN_COEFF7
NAFE13388_Base::Register24::CH_CONFIG6_15
@ CH_CONFIG6_15
NAFE13388_Base::Register24::OFFSET_COEFF12
@ OFFSET_COEFF12
NAFE13388_Base::Register24::OFFSET_COEFF14
@ OFFSET_COEFF14
NAFE13388_Base::Register24::CH_CONFIG6_0
@ CH_CONFIG6_0
NAFE13388_Base::Register24::OPT_COEF1
@ OPT_COEF1
NAFE13388_Base::Register24::OPT_COEF10
@ OPT_COEF10
NAFE13388_Base::Register24::CH_CONFIG5_14
@ CH_CONFIG5_14
NAFE13388_Base::Register24::OPT_COEF3
@ OPT_COEF3
NAFE13388_Base::Register24::SERIAL1
@ SERIAL1
NAFE13388_Base::Register24::CH_DATA0
@ CH_DATA0
NAFE13388_Base::Register24::CH_CONFIG6_1
@ CH_CONFIG6_1
NAFE13388_Base::Register24::CH_CONFIG5_12
@ CH_CONFIG5_12
NAFE13388_Base::Register24::OFFSET_COEFF2
@ OFFSET_COEFF2
NAFE13388_Base::Register24::GAIN_COEFF13
@ GAIN_COEFF13
NAFE13388_Base::Register24::OPT_COEF8
@ OPT_COEF8
NAFE13388_Base::Register24::CH_CONFIG5_13
@ CH_CONFIG5_13
NAFE13388_Base::Register24::CH_CONFIG6_6
@ CH_CONFIG6_6
NAFE13388_Base::Command
Command
Definition AFE_NXP.h:621
NAFE13388_Base::CMD_MM
@ CMD_MM
Definition AFE_NXP.h:648
NAFE13388_Base::CMD_CLEAR_DATA
@ CMD_CLEAR_DATA
Definition AFE_NXP.h:641
NAFE13388_Base::CMD_BURST_DATA
@ CMD_BURST_DATA
Definition AFE_NXP.h:651
NAFE13388_Base::CMD_RELOAD
@ CMD_RELOAD
Definition AFE_NXP.h:644
NAFE13388_Base::CMD_CH3
@ CMD_CH3
Definition AFE_NXP.h:625
NAFE13388_Base::CMD_MC
@ CMD_MC
Definition AFE_NXP.h:649
NAFE13388_Base::CMD_CH11
@ CMD_CH11
Definition AFE_NXP.h:633
NAFE13388_Base::CMD_CALC_CRC_COEF
@ CMD_CALC_CRC_COEF
Definition AFE_NXP.h:653
NAFE13388_Base::CMD_CH2
@ CMD_CH2
Definition AFE_NXP.h:624
NAFE13388_Base::CMD_MS
@ CMD_MS
Definition AFE_NXP.h:650
NAFE13388_Base::CMD_SS
@ CMD_SS
Definition AFE_NXP.h:646
NAFE13388_Base::CMD_CH8
@ CMD_CH8
Definition AFE_NXP.h:630
NAFE13388_Base::CMD_CALC_CRC_CONFG
@ CMD_CALC_CRC_CONFG
Definition AFE_NXP.h:652
NAFE13388_Base::CMD_CALC_CRC_FAC
@ CMD_CALC_CRC_FAC
Definition AFE_NXP.h:654
NAFE13388_Base::CMD_CLEAR_ALARM
@ CMD_CLEAR_ALARM
Definition AFE_NXP.h:640
NAFE13388_Base::CMD_RESET
@ CMD_RESET
Definition AFE_NXP.h:642
NAFE13388_Base::CMD_SC
@ CMD_SC
Definition AFE_NXP.h:647
NAFE13388_Base::CMD_CH5
@ CMD_CH5
Definition AFE_NXP.h:627
NAFE13388_Base::CMD_CH9
@ CMD_CH9
Definition AFE_NXP.h:631
NAFE13388_Base::CMD_CH14
@ CMD_CH14
Definition AFE_NXP.h:636
NAFE13388_Base::CMD_CH10
@ CMD_CH10
Definition AFE_NXP.h:632
NAFE13388_Base::CMD_CLEAR_REG
@ CMD_CLEAR_REG
Definition AFE_NXP.h:643
NAFE13388_Base::CMD_CH0
@ CMD_CH0
Definition AFE_NXP.h:622
NAFE13388_Base::CMD_CH13
@ CMD_CH13
Definition AFE_NXP.h:635
NAFE13388_Base::TBD
@ TBD
Definition AFE_NXP.h:645
NAFE13388_Base::CMD_CH1
@ CMD_CH1
Definition AFE_NXP.h:623
NAFE13388_Base::CMD_CH15
@ CMD_CH15
Definition AFE_NXP.h:637
NAFE13388_Base::CMD_CH7
@ CMD_CH7
Definition AFE_NXP.h:629
NAFE13388_Base::CMD_CH6
@ CMD_CH6
Definition AFE_NXP.h:628
NAFE13388_Base::CMD_ABORT
@ CMD_ABORT
Definition AFE_NXP.h:638
NAFE13388_Base::CMD_CH4
@ CMD_CH4
Definition AFE_NXP.h:626
NAFE13388_Base::CMD_CH12
@ CMD_CH12
Definition AFE_NXP.h:634
NAFE13388_Base::CMD_END
@ CMD_END
Definition AFE_NXP.h:639
NAFE13388_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition AFE_NXP.cpp:401
NAFE13388_Base::serial_number
uint64_t serial_number(void)
Definition AFE_NXP.cpp:461
NAFE13388_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition AFE_NXP.cpp:282
NAFE13388_Base::~NAFE13388_Base
virtual ~NAFE13388_Base()
Definition AFE_NXP.cpp:218
NAFE13388_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition AFE_NXP.cpp:363
NAFE13388_Base::reset
virtual void reset(bool hardware_reset=false)
Definition AFE_NXP.cpp:230
NAFE13388_Base::part_number
uint32_t part_number(void)
Definition AFE_NXP.cpp:451
NAFE13388_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
Definition AFE_NXP.cpp:357
NAFE13388_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition AFE_NXP.h:320
NAFE13388_Base::Register16
Register16
Definition AFE_NXP.h:493
NAFE13388_Base::Register16::CH_CONFIG1
@ CH_CONFIG1
NAFE13388_Base::Register16::CRC_TRIM_INT
@ CRC_TRIM_INT
NAFE13388_Base::Register16::GLOBAL_ALARM_INTERRUPT
@ GLOBAL_ALARM_INTERRUPT
NAFE13388_Base::Register16::CH_CONFIG3
@ CH_CONFIG3
NAFE13388_Base::Register16::CH_CONFIG2
@ CH_CONFIG2
NAFE13388_Base::Register16::CRC_TRIM_REGS
@ CRC_TRIM_REGS
NAFE13388_Base::Register16::GPIO_CONFIG0
@ GPIO_CONFIG0
NAFE13388_Base::Register16::PN1
@ PN1
NAFE13388_Base::Register16::CRC_COEF_REGS
@ CRC_COEF_REGS
NAFE13388_Base::Register16::GPI_EDGE_POS
@ GPI_EDGE_POS
NAFE13388_Base::Register16::CH_STATUS0
@ CH_STATUS0
NAFE13388_Base::Register16::CH_CONFIG4
@ CH_CONFIG4
NAFE13388_Base::Register16::SYS_STATUS0
@ SYS_STATUS0
NAFE13388_Base::Register16::THRS_TEMP
@ THRS_TEMP
NAFE13388_Base::Register16::PN0
@ PN0
NAFE13388_Base::Register16::GPIO_CONFIG2
@ GPIO_CONFIG2
NAFE13388_Base::Register16::GPI_DATA
@ GPI_DATA
NAFE13388_Base::Register16::GLOBAL_ALARM_ENABLE
@ GLOBAL_ALARM_ENABLE
NAFE13388_Base::Register16::DIE_TEMP
@ DIE_TEMP
NAFE13388_Base::Register16::CH_CONFIG0
@ CH_CONFIG0
NAFE13388_Base::Register16::GPIO_CONFIG1
@ GPIO_CONFIG1
NAFE13388_Base::Register16::CRC_CONF_REGS
@ CRC_CONF_REGS
NAFE13388_Base::Register16::GPO_DATA
@ GPO_DATA
NAFE13388_Base::Register16::GPI_EDGE_NEG
@ GPI_EDGE_NEG
NAFE13388_Base::Register16::PN2
@ PN2
NAFE13388_Base::Register16::CH_STATUS1
@ CH_STATUS1
NAFE13388_Base::Register16::SYS_CONFIG0
@ SYS_CONFIG0
NAFE13388_Base::temperature
float temperature(void)
Definition AFE_NXP.cpp:470
NAFE13388_Base::CalibrationError
CalibrationError
Definition AFE_NXP.h:746
NAFE13388_Base::NoError
@ NoError
Definition AFE_NXP.h:747
NAFE13388_Base::OffsetError
@ OffsetError
Definition AFE_NXP.h:749
NAFE13388_Base::GainError
@ GainError
Definition AFE_NXP.h:748
NAFE13388_UIM
Definition AFE_NXP.h:780
NAFE13388_UIM::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:638
NAFE13388_UIM::~NAFE13388_UIM
virtual ~NAFE13388_UIM()
Definition AFE_NXP.cpp:634
NAFE13388
Definition AFE_NXP.h:770
NAFE13388::~NAFE13388
virtual ~NAFE13388()
Definition AFE_NXP.cpp:623
SPI_for_AFE
Definition SPI_for_AFE.h:21
NAFE13388_Base::_ref_points
Definition AFE_NXP.h:327
NAFE13388_Base::_ref_points::coeff_index
int coeff_index
Definition AFE_NXP.h:328
NAFE13388_Base::_ref_points::high
reference_point high
Definition AFE_NXP.h:329
NAFE13388_Base::_ref_points::low
reference_point low
Definition AFE_NXP.h:330
NAFE13388_Base::_ref_points::cal_index
int cal_index
Definition AFE_NXP.h:331
NAFE13388_Base::_reference_point
Definition AFE_NXP.h:322
NAFE13388_Base::_reference_point::voltage
double voltage
Definition AFE_NXP.h:323
NAFE13388_Base::_reference_point::data
int32_t data
Definition AFE_NXP.h:324