AFE_NXP_Arduino 2.0.2 Analog Front-End (AFE) device operation sample code for Arduino

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AFE_NXP.cpp
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1
8
9#include "AFE_NXP.h"
10#include <math.h>
11
12 double AFE_base::delay_accuracy = 1.1;
13
14 void LogicalChannel_Base::enable( void )
15{
16 afe_ptr->enable_logical_channel( ch_number );
17}
18
19 void LogicalChannel_Base::disable( void )
20{
21 afe_ptr->close_logical_channel( ch_number );
22}
23
24 template<>
25 AFE_base::raw_t LogicalChannel_Base::read( void )
26{
27 return afe_ptr->start_and_read( ch_number );
28}
29
30 template<>
31 AFE_base::volt_t LogicalChannel_Base::read( void )
32{
33 AFE_base::raw_t v = read<AFE_base::raw_t>();
34 return afe_ptr->raw2v( ch_number, v );
35}
36
37LogicalChannel_Base::operator AFE_base::raw_t( void )
38{
39 return read<AFE_base::raw_t>();
40}
41
42LogicalChannel_Base::operator AFE_base::volt_t( void )
43{
44 return read<AFE_base::volt_t>();
45}
46
47 NAFE13388_Base::LogicalChannel::LogicalChannel() : LogicalChannel_Base()
48{
49}
50
51 NAFE13388_Base::LogicalChannel::~LogicalChannel()
52{
53 disable();
54}
55
56 void NAFE13388_Base::LogicalChannel::configure( const uint16_t (&cc)[ 4 ] )
57{
58 afe_ptr->open_logical_channel( ch_number, cc );
59}
60
61 void NAFE13388_Base::LogicalChannel::configure( uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
62{
63 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
64 afe_ptr->open_logical_channel( ch_number, tmp_ch_config );
65}
66
67
68/* AFE_base class ******************************************/
69
70 AFE_base::AFE_base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC ) :
71 dev_add( spi_addr ), highspeed_variant( hsv ), pin_nINT( nINT ), pin_DRDY( DRDY ), pin_SYN( SYN ), pin_nRESET( nRESET ), pin_DRDY_input( DRDY_input ), pin_SYNCDAC( SYNCDAC ), enabled_channels( 0 )
72{
73 pinMode( pin_nINT, INPUT );
74 pinMode( pin_DRDY, INPUT );
75 pinMode( pin_DRDY_input,INPUT_PULLUP );
76 pinMode( pin_SYN, OUTPUT );
77 pinMode( pin_nRESET, OUTPUT );
78 pinMode( pin_SYNCDAC, OUTPUT );
79
80 digitalWrite( pin_SYN, 1 );
81 digitalWrite( pin_nRESET, 1 );
82}
83
84 AFE_base::~AFE_base()
85{
86}
87
88 void AFE_base::init( void )
89{
90 attachInterrupt( digitalPinToInterrupt( pin_DRDY_input ), DRDY_cb, CHANGE );
91
92 drdy_flag = false;
93 set_DRDY_callback( static_default_drdy_cb );
94
95 use_DRDY_trigger( false );
96}
97
98 void AFE_base::begin( void )
99{
100 instance = this;
101
102 SPI_for_AFE::init(); // set proper SPI_CS = HIGH state. This is required for UNO R4
103
104 reset();
105 boot();
106 init();
107}
108
109 void AFE_base::set_DRDY_callback( callback_fp_t func )
110{
111 cbf_DRDY = func;
112}
113
114 void AFE_base::DRDY_cb( void )
115{
116 if ( cbf_DRDY )
117 cbf_DRDY();
118}
119
120 void AFE_base::static_default_drdy_cb( void )
121{
122 if ( nullptr != instance )
123 instance->default_drdy_cb();
124}
125
126 void AFE_base::default_drdy_cb( void )
127{
128 drdy_count++;
129 drdy_flag = true;
130}
131
132int32_t AFE_base::start_and_read( int ch )
133{
134 double wait_time = cbf_DRDY ? -1.0 : ch_delay[ ch ] * delay_accuracy;
135
136 start( ch );
137 wait_conversion_complete( wait_time );
138
139 return read( ch );
140};
141
142#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
143 void AFE_base::start_and_read( raw_t* data )
144{
145 double wait_time = cbf_DRDY ? -1.0 : total_delay * delay_accuracy;
146
147 start();
148 wait_conversion_complete( wait_time );
149
150 read( data );
151};
152 template void AFE_base::start_and_read( raw_t* data );
153#endif
154
155 int AFE_base::bit_count( uint32_t value )
156{
157 constexpr int bit_length = 32;
158 int count = 0;
159
160 for ( int i = 0; i < bit_length; i++ ) {
161 if ( value & (0x1 << i) )
162 count++;
163 }
164
165 return count;
166}
167
168 int AFE_base::wait_conversion_complete( double wait )
169{
170 if ( 0 < wait )
171 {
172 delayMicroseconds( wait * delay_accuracy * 1e6 );
173 return 0;
174 }
175
176 auto timeout_count = timeout_limit;
177
178 while ( !drdy_flag && --timeout_count )
179 ;
180
181 drdy_flag = false;
182
183 if ( !timeout_count )
184 {
185 printf( "DRDY signal wait timeout\r\n" );
186 return -1;
187 }
188 return 0;
189}
190
191 void AFE_base::use_DRDY_trigger( bool use )
192{
193 if ( use )
194 set_DRDY_callback( static_default_drdy_cb );
195 else
196 set_DRDY_callback( nullptr );
197}
198
199
200 AFE_base* AFE_base::instance = nullptr;
201 AFE_base::callback_fp_t AFE_base::cbf_DRDY = nullptr;
202
203/* NAFE13388_Base class ******************************************/
204
205 NAFE13388_Base::NAFE13388_Base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
206 : AFE_base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
207{
208 for ( auto i = 0; i < 16; i++ )
209 {
210 logical_channel[ i ].afe_ptr = this;
211 logical_channel[ i ].ch_number = i;
212 }
213}
214
215 NAFE13388_Base::~NAFE13388_Base()
216{
217}
218
219 void NAFE13388_Base::boot( void )
220{
221 command( CMD_ABORT );
222 delay( 1 );
223
224 DRDY_by_sequencer_done( true );
225}
226
227 void NAFE13388_Base::reset( bool hardware_reset )
228{
229 if ( hardware_reset )
230 {
231 digitalWrite( pin_nRESET, 0 );
232 delay( 1 );
233 digitalWrite( pin_nRESET, 1 );
234 }
235 else
236 {
237 command( CMD_RESET );
238 }
239
240 constexpr uint16_t CHIP_READY = 1 << 13;
241 constexpr auto RETRY = 10;
242
243 for ( auto i = 0; i < RETRY; i++ )
244 {
245 delay( 3 );
246 if ( reg( Register16::SYS_STATUS0 ) & CHIP_READY )
247 return;
248 }
249
250 Serial.println( "NAFE13388 couldn't get ready. Check power supply or pin conections\r\n" );
251
252 while ( true )
253 ;
254}
255
256 void NAFE13388_Base::open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] )
257{
258 command( ch );
259
260 if ( cc[ 0 ] & 0x0010 )
261 {
262 coeff_V[ ch ] = ((10.0 / (double)(1L << 24)) / pga_gain[ (cc[ 0 ] >> 5) & 0x7 ]);
263 mux_setting[ ch ] = HV_MUX;
264 }
265 else
266 {
267 coeff_V[ ch ] = ((10.0 / (double)(1L << 24)) / 2.5);
268 mux_setting[ ch ] = (cc[ 0 ] >> 1) & 0x7;
269 }
270
271 for ( auto i = 0; i < 4; i++ )
272 reg( Register16::CH_CONFIG0 + i, cc[ i ] );
273
274 enable_logical_channel( ch );
275
276 ch_delay[ ch ] = calc_delay( ch );
277}
278
279 void NAFE13388_Base::channel_info_update( uint16_t value )
280{
281 constexpr auto bit_length = 16;
282 enabled_channels = 0;
283 total_delay = 0.00;
284
285 memset( sequence_order, 0, 16 );
286
287 for ( auto i = 0; i < bit_length; i++ )
288 {
289 if ( value & (0x1 << i) )
290 {
291 sequence_order[ enabled_channels ] = i;
292 enabled_channels++;
293 total_delay += ch_delay[ i ];
294 }
295 }
296
297#if 0
298 for ( auto i = 0; i < bit_length; i++ )
299 printf( " %x", sequence_order[ i ] );
300 printf( "\r\n" );
301#endif
302}
303
304 double NAFE13388_Base::calc_delay( int ch )
305{
306 constexpr static double data_rates[] = { 288000, 192000, 144000, 96000, 72000, 48000, 36000, 24000,
307 18000, 12000, 9000, 6000, 4500, 3000, 2250, 1125,
308 562.5, 400, 300, 200, 100, 60, 50, 30,
309 25, 20, 15, 10, 7.5, };
310 constexpr static uint16_t delays[] = { 0, 2, 4, 6, 8, 10, 12, 14,
311 16, 18, 20, 28, 38, 40, 42, 56,
312 64, 76, 90, 128, 154, 178, 204, 224,
313 256, 358, 512, 716,
314 1024, 1664, 3276, 7680, 19200, 23040, };
315
316 command( ch );
317
318 uint16_t ch_config1 = reg( Register16::CH_CONFIG1 );
319 uint16_t ch_config2 = reg( Register16::CH_CONFIG2 );
320
321 uint8_t adc_data_rate = (ch_config1 >> 3) & 0x001F;
322 uint8_t adc_sinc = (ch_config1 >> 0) & 0x0007;
323 uint8_t ch_delay = (ch_config2 >> 10) & 0x003F;
324 bool adc_normal_setting = (ch_config2 >> 9) & 0x0001;
325 bool ch_chop = (ch_config2 >> 7) & 0x0001;
326
327 double base_freq = data_rates[ adc_data_rate ];
328 double delay_setting = delays[ ch_delay ] / 4608000.00;
329
330 if ( highspeed_variant )
331 {
332 base_freq *= 2.00;
333 delay_setting /= 2.00;
334 }
335
336 if ( (28 < adc_data_rate) || (4 < adc_sinc) || ((adc_data_rate < 12) && (adc_sinc)) )
337 return 0.00;
338
339 if ( !adc_normal_setting )
340 base_freq /= (adc_sinc + 1);
341
342 if ( ch_chop )
343 base_freq /= 2;
344
345#if 0
346 printf( "base_freq = %lf\r\n", base_freq );
347 printf( "delay_setting = %lf\r\n", delay_setting );
348 printf( "total delay = %lf\r\n", (1 / base_freq) + delay_setting );
349#endif
350
351 return (1 / base_freq) + delay_setting;
352}
353
354 void NAFE13388_Base::open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
355{
356 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
357 open_logical_channel( ch, tmp_ch_config );
358}
359
360 void NAFE13388_Base::enable_logical_channel( int ch )
361{
362 const uint16_t setbit = 0x1 << ch;
363 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~setbit, setbit );
364
365 channel_info_update( bits );
366}
367
368 void NAFE13388_Base::close_logical_channel( int ch )
369{
370 const uint16_t clearingbit = 0x1 << ch;
371 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~clearingbit, ~clearingbit );
372
373 channel_info_update( bits );
374}
375
376 void NAFE13388_Base::close_logical_channel( void )
377{
378 reg( Register16::CH_CONFIG4, 0x0000 );
379 channel_info_update( 0x0000 );
380}
381
382 void NAFE13388_Base::start( int ch )
383{
384 command( ch );
385 command( Command::CMD_SS );
386}
387
388 void NAFE13388_Base::start( void )
389{
390 command( Command::CMD_MM );
391}
392
393 void NAFE13388_Base::start_continuous_conversion( void )
394{
395 command( Command::CMD_MC );
396}
397
398 void NAFE13388_Base::DRDY_by_sequencer_done( bool flag )
399{
400 bit_op( Register16::SYS_CONFIG0, ~0x0010, flag ? 0x0010 : 0x00 );
401}
402
403int32_t NAFE13388_Base::read( int ch )
404{
405 return reg( Register24::CH_DATA0 + ch );
406}
407
408 void NAFE13388_Base::read( raw_t *data )
409{
410 burst( (uint32_t *)data, enabled_channels );
411}
412
413 void NAFE13388_Base::read( volt_t *data )
414{
415 raw_t raw_data[ 16 ];
416
417 read( raw_data );
418
419 for ( auto i = 0; i < enabled_channels; i++ )
420 data[ i ] = raw2v( sequence_order[ i ], raw_data[ i ] );
421}
422
423 void NAFE13388_Base::command( uint16_t com )
424{
425 write_r16( com );
426}
427
428 void NAFE13388_Base::reg( Register16 r, uint16_t value )
429{
430 write_r16( static_cast<uint16_t>( r ), value );
431}
432
433 void NAFE13388_Base::reg( Register24 r, uint32_t value )
434{
435 write_r24( static_cast<uint16_t>( r ), value );
436}
437
438uint16_t NAFE13388_Base::reg( Register16 r )
439{
440 return read_r16( static_cast<uint16_t>( r ) );
441}
442
443uint32_t NAFE13388_Base::reg( Register24 r )
444{
445 return read_r24( static_cast<uint16_t>( r ) );
446}
447
448uint32_t NAFE13388_Base::part_number( void )
449{
450 return (static_cast<uint32_t>( reg( Register16::PN2 ) ) << 16) | reg( Register16::PN1 );
451}
452
453uint8_t NAFE13388_Base::revision_number( void )
454{
455 return reg( Register16::PN0 ) & 0xF;
456}
457
458uint64_t NAFE13388_Base::serial_number( void )
459{
460 uint64_t serial_number;
461
462 serial_number = reg( Register24::SERIAL1 );
463 serial_number <<= 24;
464 return serial_number | reg( Register24::SERIAL0 );
465}
466
467 float NAFE13388_Base::temperature( void )
468{
469 return ((int16_t)reg( Register16::DIE_TEMP )) / 64.0;
470}
471
472 void NAFE13388_Base::gain_offset_coeff( const ref_points &ref )
473{
474 constexpr double pga1x_voltage = 5.0;
475 constexpr int adc_resolution = 24;
476 constexpr double pga_gain_setting = 0.2;
477
478 constexpr double fullscale_voltage = pga1x_voltage / pga_gain_setting;
479
480 double fullscale_data = pow( 2, (adc_resolution - 1) );
481 double ref_data_span = ref.high.data - ref.low.data;
482 double ref_voltage_span = ref.high.voltage - ref.low.voltage;
483
484 double dv_slope = ref_data_span / ref_voltage_span;
485 double custom_gain = dv_slope * (fullscale_voltage / fullscale_data);
486 double custom_offset = (dv_slope * ref.low.voltage - ref.low.data) / custom_gain;
487
488 int32_t gain_coeff_cal = reg( Register24::GAIN_COEFF0 + ref.cal_index );
489 int32_t offsset_coeff_cal = reg( Register24::OFFSET_COEFF0 + ref.cal_index );
490 int32_t gain_coeff_new = round( gain_coeff_cal * custom_gain );
491 int32_t offset_coeff_new = round( custom_offset - offsset_coeff_cal );
492
493#if 0
494 printf( "ref_point_high = %8ld @%6.3lf\r\n", ref.high.data, ref.high.voltage );
495 printf( "ref_point_low = %8ld @%6.3lf\r\n", ref.low.data, ref.low.voltage );
496 printf( "gain_coeff_new = %8ld\r\n", gain_coeff_new );
497 printf( "offset_coeff_new = %8ld\r\n", offset_coeff_new );
498#endif
499
500 reg( Register24::GAIN_COEFF0 + ref.coeff_index, gain_coeff_new );
501 reg( Register24::OFFSET_COEFF0 + ref.coeff_index, offset_coeff_new );
502}
503
504 int NAFE13388_Base::self_calibrate( int pga_gain_index, int channel_selection, int input_select, double reference_source_voltage, bool use_positive_side )
505{
506 constexpr auto low_gain_index = 2;
507 auto channel_in_use = false;
508 ch_setting_t tmp_ch_config;
509 int gain_index = static_cast<int>( pga_gain_index );
510
511 // logical channel selection to perform the self-calibration
512 // if the chennel in-use, save channel setting to temporal memory
513
514 if ( reg( Register16::CH_CONFIG4 ) & (0x1 << channel_selection) )
515 {
516 channel_in_use = true;
517
518 command( channel_selection );
519
520 for ( auto i = 0; i < 4; i++ )
521 tmp_ch_config[ i ] = reg( Register16::CH_CONFIG0 + i );
522 }
523
524 // if user doesn't specify the channel and voltage, use REFH or REFL
525
526 if ( !input_select )
527 {
528 bool low_gain = (gain_index <= low_gain_index);
529
530 input_select = low_gain ? 0x5 : 0x6;
531 reference_source_voltage = (reg( low_gain ? Register24::OPT_COEF1 : Register24::OPT_COEF2 ) * 5.00) / (double)(1UL << 24);
532
533#if 1
534 printf( "==== self-calibration for PGA gain setting: x%3.1lf\r\n", pga_gain[ gain_index ] );
535 printf( "gain = %s\r\n", low_gain ? "low" : "high" );
536 printf( "REF%s = %10.8lfV\r\n", low_gain ? "H" : "L", reference_source_voltage );
537#endif
538 }
539
540 // logical channel settings
541 // Total 3 settings are prepared to measure reference_voltage, internal-GND and AICOM
542
543 const uint16_t REF_GND = 0x0011 | (gain_index << 5);
544 const uint16_t REF_V = (input_select << (use_positive_side ? 12 : 8)) | REF_GND;
545 const uint16_t REF_COM = 0x7700 | REF_GND;
546 const uint16_t ch_config1 = (gain_index << 12) | 0x00E4;
547 constexpr uint16_t ch_config2 = 0x8480;
548 constexpr uint16_t ch_config3 = 0x0000;
549
550 const ch_setting_t refh = { REF_V, ch_config1, ch_config2, ch_config3 };
551 const ch_setting_t refg = { REF_GND, ch_config1, ch_config2, ch_config3 };
552 const ch_setting_t refc = { REF_COM, ch_config1, ch_config2 & ~0x0080, ch_config3 }; //CH_CHOP:off
553
554 // forcing to set unity-gain and zero-offset
555
556 constexpr raw_t default_gain_coeff_value = 0x1UL << 22;
557 constexpr raw_t default_offset_coeff_value = 0;
558
559 reg( Register24::GAIN_COEFF0 + gain_index, default_gain_coeff_value );
560 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value );
561
562 // measure the logical channel with those different 3 settings
563
564 open_logical_channel( channel_selection, refh );
565 raw_t data_REF = start_and_read( channel_selection );
566
567 open_logical_channel( channel_selection, refg );
568 raw_t data_GND = start_and_read( channel_selection );
569
570 open_logical_channel( channel_selection, refc );
571 raw_t data_COM = start_and_read( channel_selection );
572
573 // calculation
574
575 const double fullscale_voltage = 5.00 / pga_gain[ gain_index ];
576 const double calibrated_gain = (double)(0x1UL << 23) * (reference_source_voltage / fullscale_voltage) / (double)(data_REF - data_GND);
577
578#if 0
579 printf( "data_REF = %8ld (%lfV)\r\n", data_REF, raw2v( channel_selection, data_REF ) );
580 printf( "data_GND = %8ld (%lfmV)\r\n", data_GND, raw2mv( channel_selection, data_GND ) );
581 printf( "data_COM = %8ld (%lfmV)\r\n", data_COM, raw2mv( channel_selection, data_COM ) );
582 printf( "gain adjustment = %8lf (%lfdB)\r\n\r\n", calibrated_gain, 20 * log10( calibrated_gain ) );
583#endif
584
585 if ( !( (0.95 < calibrated_gain) && (calibrated_gain < 1.05) ) )
586 return CalibrationError::GainError;
587
588 const double offset_mv = raw2mv( channel_selection, data_COM );
589
590 if ( !( (-10.0 < offset_mv) && (offset_mv < 10.0) ) )
591 return CalibrationError::OffsetError;
592
593 // setting registers: GAIN_COEFF[n] and OFFSET_COEFF[n]
594
595 reg( Register24::GAIN_COEFF0 + gain_index, (uint32_t)(default_gain_coeff_value * calibrated_gain) );
596 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value + data_COM );
597
598 // if the channel was in-use, revert the setting
599
600 if ( channel_in_use )
601 open_logical_channel( channel_selection, tmp_ch_config );
602 else
603 close_logical_channel( channel_selection );
604
605 return CalibrationError::NoError;
606}
607
608 void NAFE13388_Base::blink_leds( void )
609{
610}
611
612
613/* NAFE13388 class ******************************************/
614
615 NAFE13388::NAFE13388( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
616 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
617{
618}
619
620 NAFE13388::~NAFE13388()
621{
622}
623
624/* NAFE13388_UIM class ******************************************/
625
626 NAFE13388_UIM::NAFE13388_UIM( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
627 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
628{
629}
630
631 NAFE13388_UIM::~NAFE13388_UIM()
632{
633}
634
635 void NAFE13388_UIM::blink_leds( void )
636{
637 uint16_t pattern[] = {
638 0x8000, 0x0040, 0x0100, 0x0080, 0x0200, 0x0400, 0x0800, 0x1000,
639 0x2000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0080,
640 0x0100, 0x0040,
641 };
642 reg( Register16::GPIO_CONFIG0, 0xFFC0 );
643 reg( Register16::GPIO_CONFIG1, 0xFFC0 );
644 reg( Register16::GPIO_CONFIG2, 0x0000 );
645
646 for ( auto j = 0; j < 2; j++ )
647 {
648 for ( auto i = 0U; i < sizeof( pattern ) / sizeof( uint16_t ); i++ )
649 {
650 reg( Register16::GPO_DATA, pattern[ i ] );
651 delay( 20 );
652 }
653 }
654
655 uint16_t pv = 0;
656
657 for ( auto j = 0; j < 4; j++ )
658 {
659 for ( auto i = 0; i < 10; i++ )
660 {
661 pv = (j % 2) ? pv & ~pattern[ i ] : pv | pattern[ i ];
662 reg( Register16::GPO_DATA, pv ); delay( 20 );
663 }
664 }
665}
666
667 double NAFE13388_Base::pga_gain[] = { 0.2, 0.4, 0.8, 1, 2, 4, 8, 16 };
668
AFE_NXP.h
AFE_base
Definition AFE_NXP.h:18
AFE_base::instance
static AFE_base * instance
Definition AFE_NXP.h:258
AFE_base::cbf_DRDY
static callback_fp_t cbf_DRDY
Definition AFE_NXP.h:250
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::volt_t
double volt_t
Definition AFE_NXP.h:23
AFE_base::use_DRDY_trigger
void use_DRDY_trigger(bool use=true)
Definition AFE_NXP.cpp:191
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Definition AFE_NXP.cpp:84
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Definition AFE_NXP.cpp:114
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Definition AFE_NXP.h:217
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Definition AFE_NXP.cpp:109
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Definition AFE_NXP.h:221
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Definition AFE_NXP.cpp:88
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Definition AFE_NXP.h:244
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Definition AFE_NXP.cpp:98
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Definition AFE_NXP.h:174
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Definition AFE_NXP.h:156
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Definition AFE_NXP.h:216
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Definition AFE_NXP.h:248
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Definition AFE_NXP.cpp:155
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Definition AFE_NXP.h:222
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Definition AFE_NXP.cpp:126
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Definition AFE_NXP.h:46
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Definition AFE_NXP.h:234
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Definition AFE_NXP.cpp:132
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Definition AFE_NXP.h:228
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Definition AFE_NXP.h:231
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Definition AFE_NXP.cpp:120
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Definition AFE_NXP.cpp:70
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Definition AFE_NXP.cpp:168
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Definition AFE_NXP.h:249
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Definition AFE_NXP.h:219
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Definition AFE_NXP.h:242
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Definition AFE_NXP.h:240
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Definition AFE_NXP.h:237
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Definition AFE_NXP.h:220
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Definition AFE_NXP.h:215
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Definition AFE_NXP.h:218
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Definition AFE_NXP.h:241
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Definition AFE_NXP.h:264
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Definition AFE_NXP.cpp:14
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Definition AFE_NXP.h:285
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Definition AFE_NXP.h:284
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Definition AFE_NXP.cpp:19
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Definition AFE_NXP.cpp:51
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Definition AFE_NXP.cpp:47
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Definition AFE_NXP.cpp:56
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Definition AFE_NXP.cpp:393
NAFE13388_Base::raw2v
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Definition AFE_NXP.h:410
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Definition AFE_NXP.cpp:219
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Definition AFE_NXP.cpp:472
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Definition AFE_NXP.cpp:304
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Definition AFE_NXP.cpp:423
NAFE13388_Base::blink_leds
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Definition AFE_NXP.cpp:608
NAFE13388_Base::read
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Definition AFE_NXP.cpp:403
NAFE13388_Base::logical_channel
LogicalChannel logical_channel[16]
Definition AFE_NXP.h:344
NAFE13388_Base::pga_gain
static double pga_gain[]
Definition AFE_NXP.h:667
NAFE13388_Base::bit_op
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Definition AFE_NXP.h:660
NAFE13388_Base::self_calibrate
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Definition AFE_NXP.cpp:504
NAFE13388_Base::ref_points
struct NAFE13388_Base::_ref_points ref_points
NAFE13388_Base::start
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Definition AFE_NXP.cpp:388
NAFE13388_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition AFE_NXP.cpp:428
NAFE13388_Base::revision_number
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Definition AFE_NXP.cpp:453
NAFE13388_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition AFE_NXP.cpp:376
NAFE13388_Base::Register24
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Definition AFE_NXP.h:482
NAFE13388_Base::Register24::OFFSET_COEFF0
@ OFFSET_COEFF0
Definition AFE_NXP.h:546
NAFE13388_Base::Register24::GAIN_COEFF0
@ GAIN_COEFF0
Definition AFE_NXP.h:530
NAFE13388_Base::Register24::OPT_COEF2
@ OPT_COEF2
Definition AFE_NXP.h:564
NAFE13388_Base::Register24::SERIAL0
@ SERIAL0
Definition AFE_NXP.h:577
NAFE13388_Base::Register24::OPT_COEF1
@ OPT_COEF1
Definition AFE_NXP.h:563
NAFE13388_Base::Register24::SERIAL1
@ SERIAL1
Definition AFE_NXP.h:576
NAFE13388_Base::Register24::CH_DATA0
@ CH_DATA0
Definition AFE_NXP.h:483
NAFE13388_Base::CMD_MM
@ CMD_MM
Definition AFE_NXP.h:607
NAFE13388_Base::CMD_MC
@ CMD_MC
Definition AFE_NXP.h:608
NAFE13388_Base::CMD_SS
@ CMD_SS
Definition AFE_NXP.h:605
NAFE13388_Base::CMD_RESET
@ CMD_RESET
Definition AFE_NXP.h:601
NAFE13388_Base::CMD_ABORT
@ CMD_ABORT
Definition AFE_NXP.h:597
NAFE13388_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition AFE_NXP.cpp:398
NAFE13388_Base::serial_number
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Definition AFE_NXP.cpp:458
NAFE13388_Base::channel_info_update
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Definition AFE_NXP.cpp:279
NAFE13388_Base::~NAFE13388_Base
virtual ~NAFE13388_Base()
Definition AFE_NXP.cpp:215
NAFE13388_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition AFE_NXP.cpp:360
NAFE13388_Base::reset
virtual void reset(bool hardware_reset=false)
Definition AFE_NXP.cpp:227
NAFE13388_Base::part_number
uint32_t part_number(void)
Definition AFE_NXP.cpp:448
NAFE13388_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
Definition AFE_NXP.cpp:354
NAFE13388_Base::NAFE13388_Base
NAFE13388_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition AFE_NXP.cpp:205
NAFE13388_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition AFE_NXP.h:291
NAFE13388_Base::Register16
Register16
Definition AFE_NXP.h:452
NAFE13388_Base::Register16::CH_CONFIG1
@ CH_CONFIG1
Definition AFE_NXP.h:454
NAFE13388_Base::Register16::CH_CONFIG2
@ CH_CONFIG2
Definition AFE_NXP.h:455
NAFE13388_Base::Register16::GPIO_CONFIG0
@ GPIO_CONFIG0
Definition AFE_NXP.h:462
NAFE13388_Base::Register16::PN1
@ PN1
Definition AFE_NXP.h:477
NAFE13388_Base::Register16::CH_CONFIG4
@ CH_CONFIG4
Definition AFE_NXP.h:457
NAFE13388_Base::Register16::SYS_STATUS0
@ SYS_STATUS0
Definition AFE_NXP.h:469
NAFE13388_Base::Register16::PN0
@ PN0
Definition AFE_NXP.h:478
NAFE13388_Base::Register16::GPIO_CONFIG2
@ GPIO_CONFIG2
Definition AFE_NXP.h:464
NAFE13388_Base::Register16::DIE_TEMP
@ DIE_TEMP
Definition AFE_NXP.h:472
NAFE13388_Base::Register16::CH_CONFIG0
@ CH_CONFIG0
Definition AFE_NXP.h:453
NAFE13388_Base::Register16::GPIO_CONFIG1
@ GPIO_CONFIG1
Definition AFE_NXP.h:463
NAFE13388_Base::Register16::GPO_DATA
@ GPO_DATA
Definition AFE_NXP.h:467
NAFE13388_Base::Register16::PN2
@ PN2
Definition AFE_NXP.h:476
NAFE13388_Base::Register16::SYS_CONFIG0
@ SYS_CONFIG0
Definition AFE_NXP.h:468
NAFE13388_Base::temperature
float temperature(void)
Definition AFE_NXP.cpp:467
NAFE13388_Base::NoError
@ NoError
Definition AFE_NXP.h:704
NAFE13388_Base::OffsetError
@ OffsetError
Definition AFE_NXP.h:706
NAFE13388_Base::GainError
@ GainError
Definition AFE_NXP.h:705
NAFE13388_UIM::NAFE13388_UIM
NAFE13388_UIM(bool spi_addr=0, bool highspeed_variant=false, int nINT=3, int DRDY=4, int SYN=6, int nRESET=7, int DRDY_input=2, int SYNCDAC=14)
Definition AFE_NXP.cpp:626
NAFE13388_UIM::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:635
NAFE13388_UIM::~NAFE13388_UIM
virtual ~NAFE13388_UIM()
Definition AFE_NXP.cpp:631
NAFE13388::~NAFE13388
virtual ~NAFE13388()
Definition AFE_NXP.cpp:620
NAFE13388::NAFE13388
NAFE13388(bool spi_addr=0, bool highspeed_variant=false, int nINT=2, int DRDY=4, int SYN=5, int nRESET=6, int DRDY_input=15, int SYNCDAC=14)
Definition AFE_NXP.cpp:615
SPI_for_AFE::read_r24
int32_t read_r24(uint16_t reg)
Definition SPI_for_AFE.cpp:48
SPI_for_AFE::init
void init(void)
Definition SPI_for_AFE.cpp:73
SPI_for_AFE::write_r24
void write_r24(uint16_t reg, uint32_t val)
Definition SPI_for_AFE.cpp:40
SPI_for_AFE::read_r16
uint16_t read_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:29
SPI_for_AFE::burst
void burst(uint32_t *data, int length, int width=3)
Definition SPI_for_AFE.cpp:59
SPI_for_AFE::write_r16
void write_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:13
NAFE13388_Base::_ref_points::coeff_index
int coeff_index
Definition AFE_NXP.h:299
NAFE13388_Base::_ref_points::high
reference_point high
Definition AFE_NXP.h:300
NAFE13388_Base::_ref_points::low
reference_point low
Definition AFE_NXP.h:301
NAFE13388_Base::_ref_points::cal_index
int cal_index
Definition AFE_NXP.h:302
NAFE13388_Base::_reference_point::voltage
double voltage
Definition AFE_NXP.h:294
NAFE13388_Base::_reference_point::data
int32_t data
Definition AFE_NXP.h:295