AFE_NXP_Arduino 2.0.2 Analog Front-End (AFE) device operation sample code for Arduino

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NAFE33352.cpp
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1
8
9#include "NAFE33352.h"
10#include <Arduino.h>
11#include <math.h>
12
13 NAFE33352_Base::LogicalChannel::LogicalChannel() : LogicalChannel_Base()
14{
15}
16
17 NAFE33352_Base::LogicalChannel::~LogicalChannel()
18{
19 disable();
20}
21
22 void NAFE33352_Base::LogicalChannel::configure( const uint16_t (&cc)[ 3 ] )
23{
24 const uint16_t tmp_ch_config[ 4 ] = { cc[ 0 ], cc[ 1 ], cc[ 2 ], 0 };
25 afe_ptr->open_logical_channel( ch_number, tmp_ch_config );
26}
27
28 void NAFE33352_Base::LogicalChannel::configure( uint16_t cc0, uint16_t cc1, uint16_t cc2 )
29{
30 const uint16_t tmp_ch_config[ 4 ] = { cc0, cc1, cc2, 0 };
31 afe_ptr->open_logical_channel( ch_number, tmp_ch_config );
32}
33
34 NAFE33352_Base::DAC::DAC()
35{
36}
37
38 NAFE33352_Base::DAC::~DAC()
39{
40}
41
42 void NAFE33352_Base::DAC::configure( uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3, uint16_t cc4, uint16_t cc5 )
43{
44 const uint16_t tmp_ch_config[ 6 ] = { cc0, cc1, cc2, cc3, cc4, cc5 };
45 afe_ptr->open_dac_output( tmp_ch_config );
46}
47
48 void NAFE33352_Base::DAC::configure( const uint16_t (&cc)[ 6 ] )
49{
50 afe_ptr->open_dac_output( cc );
51}
52
53 void NAFE33352_Base::DAC::configure( ModeSelect mode, double full_scale_range )
54{
55 uint16_t default_dac_setting[ 6 ] = { 0x0000, 0x1000, 0x87FF, 0x8200, 0xE7FF, 0x0C00 };
56
57 output_mode = mode;
58
59 switch ( output_mode )
60 {
61 case NAFE33352_Base::DAC::ModeSelect::OFF:
62 full_scale = 12.50;
63 default_dac_setting[ 0 ] |= 0x0002;
64 break;
65 case NAFE33352_Base::DAC::ModeSelect::VOLTAGE:
66 full_scale = 12.50;
67 default_dac_setting[ 0 ] |= 0x6040;
68 break;
69 case NAFE33352_Base::DAC::ModeSelect::CURRENT:
70 full_scale = 0.025 / 0.95;
71 default_dac_setting[ 0 ] |= 0x6061;
72 default_dac_setting[ 1 ] |= 0x1000;
73 break;
74 case NAFE33352_Base::DAC::ModeSelect::CURRENT_RECAL:
75 full_scale = 0.025;
76 default_dac_setting[ 0 ] |= 0x6061;
77 default_dac_setting[ 1 ] |= 0x1000;
78 break;
79 case NAFE33352_Base::DAC::ModeSelect::DAC_OFF_VOLTAGE_IN:
80 full_scale = 0.025;
81 default_dac_setting[ 0 ] |= 0x6000;
82 break;
83 case NAFE33352_Base::DAC::ModeSelect::DAC_OFF_CURRENT_IN:
84 full_scale = 0.025;
85 default_dac_setting[ 0 ] |= 0x7000;
86 break;
87 }
88
89 if ( 0.0 < full_scale_range ) // overwrite fullscale range if it is specified
90 full_scale = full_scale_range;
91
92 configure( default_dac_setting );
93}
94
95 void NAFE33352_Base::DAC::configure( double full_scale_range )
96{
97 full_scale = full_scale_range;
98}
99
100 void NAFE33352_Base::DAC::output( double value )
101{
102 afe_ptr->dac_out( value, full_scale, 18 );
103}
104
105 NAFE33352_Base::DAC& NAFE33352_Base::DAC::operator=( double value )
106{
107 output( value );
108 return *this;
109}
110
111
112
113/* NAFE33352_Base class ******************************************/
114
115 NAFE33352_Base::NAFE33352_Base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
116 : AFE_base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
117{
118 for ( auto i = 0; i < 16; i++ )
119 {
120 logical_channel[ i ].afe_ptr = this;
121 logical_channel[ i ].ch_number = i;
122 }
123
124 dac.afe_ptr = this;
125}
126
127 NAFE33352_Base::~NAFE33352_Base()
128{
129}
130
131 void NAFE33352_Base::boot( void )
132{
133 command( NAFE33352_Base::Command::CMD_ADC_ABORT );
134 command( NAFE33352_Base::Command::CMD_AO_ABORT );
135 delay( 1 );
136
137 DRDY_by_sequencer_done( true );
138
139 reg( NAFE33352_Base::Register16::SYS_CONFIG, 0x0000 );
140 reg( NAFE33352_Base::Register16::CK_SRC_SEL_CONFIG, 0x0000 );
141
142 reg( NAFE33352_Base::Register16::AI_SYSCFG, 0x0800 );
143
144
145}
146
147 void NAFE33352_Base::reset( bool hardware_reset )
148{
149 if ( hardware_reset )
150 Serial.println( "warning: UIOM doesn't have hardware RESET pin on the board. This reset will be ignored\r\n" );
151
152 command( NAFE33352_Base::Command::CMD_RESET );
153
154 constexpr uint16_t CHIP_READY = 1 << 13;
155 constexpr auto RETRY = 10;
156
157 for ( auto i = 0; i < RETRY; i++ )
158 {
159 delay( 1 );
160 if ( reg( NAFE33352_Base::Register16::SYS_STATUS ) & CHIP_READY )
161 return;
162 }
163
164 Serial.println( "NAFE33352 couldn't get ready. Check power supply or pin conections\r\n" );
165
166 while ( true )
167 ;
168
169}
170
171 void NAFE33352_Base::open_dac_output( const uint16_t (&cc)[ 6 ] )
172{
173 for ( auto i = 0; i < 6; i++ )
174 reg( NAFE33352_Base::Register16::AIO_CONFIG + i, cc[ i ] );
175}
176
177
178 void NAFE33352_Base::open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] )
179{
180 static bool pga_enabled = false;
181 constexpr double pow2_24 = (double)(1L << 24);
182 double coeff = 0.00;
183 bool pga_on = false;
184
185 mux_setting[ ch ] = (cc[ 0 ] >> 3) & 0x1F;
186
187 command( NAFE33352_Base::Command::CMD_CH0 + ch );
188
189 switch ( mux_setting[ ch ] )
190 {
191 case VCM_VCM:
192 case GPIO0_GPIO1:
193 coeff = (20.00 * 2.50) / (12.5 * pow2_24);
194 break;
195 case AIP_AIN:
196 coeff = (20.00 * 2.50) / ((cc[ 0 ] & 0x0100 ? 16.00 : 1.00) * pow2_24);
197 pga_on = true;
198 break;
199 case AIP_VSNS:
200 case VSNS:
201 coeff = (20.00 * 2.50) / pow2_24;
202 pga_on = true;
203 break;
204 case AIP:
205 case AIN:
206 coeff = (20.00 * 2.50) / ((cc[ 0 ] & 0x0100 ? 16.00 : 1.00) * pow2_24);
207 pga_on = true;
208 break;
209 case ISNS:
210 coeff = (20.00 * 2.50) / (3.7989 * pow2_24);
211 break;
212 case TIA:
213 coeff = (20.00 * 2.50) / (2.50 * pow2_24);
214 break;
215 case GPIO0_VCM:
216 case VCM_GPIO1:
217 case REF_BYP__VCM:
218 case LDO:
219 case DAC_REF:
220 coeff = (20.00 * 2.50) / (12.5 * pow2_24) + 1.50;
221 break;
222 case VCM__REF_BYP:
223 coeff = (20.00 * 2.50) / (12.5 * pow2_24) - 1.50;
224 break;
225 case BG:
226 //coeff = (20.00 * 2.50) / (12.5 * pow2_24) - 1.50;
227 break;
228 case VADD:
229 coeff = (2.00 * 20.00 * 2.50) / (12.5 * pow2_24) - 1.50;
230 break;
231 case VHDD:
232 case VHSS:
233 coeff = (40.00 * 20.00 * 2.50) / (12.5 * pow2_24);
234 break;
235 }
236
237 coeff_V[ ch ] = coeff;
238
239 if ( pga_on && !pga_enabled )
240 {
241 reg( NAFE33352_Base::Register16::AI_SYSCFG, 0x0800 );
242 pga_enabled = true;
243 }
244
245 for ( auto i = 0; i < 3; i++ )
246 reg( NAFE33352_Base::Register16::AI_CONFIG0 + i, cc[ i ] );
247
248 enable_logical_channel( ch );
249
250 ch_delay[ ch ] = calc_delay( ch );
251
252#if 0
253 Serial.print("lc[ ");
254 Serial.print(ch);
255 Serial.print("] : ");
256 Serial.println( ch_delay[ ch ], 10 );
257#endif
258}
259
260 void NAFE33352_Base::channel_info_update( uint16_t value )
261{
262 constexpr auto bit_length = 16;
263 enabled_channels = 0;
264 total_delay = 0.00;
265
266 memset( sequence_order, 0, 16 );
267
268 for ( auto i = 0; i < bit_length; i++ )
269 {
270 if ( value & (0x1 << i) )
271 {
272 sequence_order[ enabled_channels ] = i;
273 enabled_channels++;
274 total_delay += ch_delay[ i ];
275 }
276 }
277
278#if 0
279 for ( auto i = 0; i < bit_length; i++ )
280 printf( " %x", sequence_order[ i ] );
281 printf( "\r\n" );
282#endif
283}
284
285 double NAFE33352_Base::calc_delay( int ch )
286{
287 constexpr double system_clock = 4608000.00;
288
289 constexpr static double data_rates[] = { 288000, 192000, 144000, 96000, 72000, 48000, 36000, 24000,
290 18000, 12000, 9000, 6000, 4500, 3000, 2250, 1125,
291 562.5, 400, 300, 200, 100, 60, 50, 30,
292 25, 20, 15, 10, 7.5, };
293 constexpr static uint16_t delays[] = { 0, 2, 4, 6, 8, 10, 12, 14,
294 16, 18, 20, 28, 38, 40, 42, 56,
295 64, 76, 90, 128, 154, 178, 204, 224,
296 256, 358, 512, 716,
297 1024, 1664, 3276, 7680, 19200, 23040, };
298
299 command( NAFE33352_Base::Command::CMD_CH0 + ch );
300
301 uint16_t ch_config1 = reg( NAFE33352_Base::Register16::AI_CONFIG1 );
302 uint16_t ch_config2 = reg( NAFE33352_Base::Register16::AI_CONFIG2 );
303
304 uint8_t adc_data_rate = (ch_config1 >> 3) & 0x001F;
305 uint8_t adc_sinc = (ch_config1 >> 0) & 0x0007;
306 uint8_t ch_delay = (ch_config2 >> 10) & 0x003F;
307 bool adc_normal_setting = (ch_config2 >> 9) & 0x0001;
308 bool ch_chop = (ch_config2 >> 7) & 0x0001;
309 double base_freq = data_rates[ adc_data_rate ];
310 double delay_setting = ((double)delays[ ch_delay ]) / system_clock;
311
312 if ( highspeed_variant )
313 {
314 base_freq *= 2.00;
315 delay_setting /= 2.00;
316 }
317
318 if ( (28 < adc_data_rate) || (4 < adc_sinc) || ((adc_data_rate < 12) && (adc_sinc)) )
319 return 0.00;
320
321 if ( !adc_normal_setting )
322 base_freq /= (adc_sinc + 1);
323
324 if ( ch_chop )
325 base_freq /= 2;
326
327#if 0
328 Serial.print( "adc_data_rate =" );
329 Serial.println( adc_data_rate );
330 Serial.print( "base_freq = " );
331 Serial.println( base_freq );
332 Serial.print( "delay_setting = " );
333 Serial.println( delay_setting, 10 );
334 Serial.print( "channel delay = " );
335 Serial.println( (1 / base_freq) + delay_setting, 10 );
336#endif
337
338 return (1 / base_freq) + delay_setting;
339}
340
341#pragma GCC diagnostic ignored "-Wunused-parameter"
342 void NAFE33352_Base::open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t dummy )
343{
344 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2 };
345 open_logical_channel( ch, tmp_ch_config );
346}
347#pragma GCC diagnostic pop
348
349 void NAFE33352_Base::enable_logical_channel( int ch )
350{
351 const uint16_t setbit = 0x1 << (ch + 8);
352 const uint16_t bits = bit_op( NAFE33352_Base::Register16::AI_MULTI_CH_EN, ~setbit, setbit );
353
354 channel_info_update( bits >> 8 );
355}
356
357 void NAFE33352_Base::close_logical_channel( int ch )
358{
359 const uint16_t clearingbit = 0x1 << (ch + 8);
360 const uint16_t bits = bit_op( NAFE33352_Base::Register16::AI_MULTI_CH_EN, ~clearingbit, ~clearingbit );
361
362 channel_info_update( bits >> 8 );
363}
364
365 void NAFE33352_Base::close_logical_channel( void )
366{
367 reg( NAFE33352_Base::Register16::AI_MULTI_CH_EN, 0x0000 );
368 channel_info_update( 0x0000 );
369}
370
371 void NAFE33352_Base::start( int ch )
372{
373 command( NAFE33352_Base::Command::CMD_CH0 + ch );
374 command( NAFE33352_Base::Command::CMD_SS );
375}
376
377 void NAFE33352_Base::start( void )
378{
379 command( NAFE33352_Base::Command::CMD_MM );
380}
381
382 void NAFE33352_Base::start_continuous_conversion( void )
383{
384 command( NAFE33352_Base::Command::CMD_MC );
385}
386
387 void NAFE33352_Base::DRDY_by_sequencer_done( bool flag )
388{
389 bit_op( NAFE33352_Base::Register16::AI_SYSCFG, ~0x0100, flag ? 0x0100 : 0x0000 );
390}
391
392int32_t NAFE33352_Base::read( int ch )
393{
394 return reg( NAFE33352_Base::Register24::AI_DATA0 + ch );
395}
396
397 void NAFE33352_Base::read( raw_t *data )
398{
399 burst( (uint32_t *)data, enabled_channels );
400}
401
402 void NAFE33352_Base::read( volt_t *data )
403{
404 raw_t raw_data[ 16 ];
405
406 read( raw_data );
407
408 for ( auto i = 0; i < enabled_channels; i++ )
409 data[ i ] = raw2uv( sequence_order[ i ], raw_data[ i ] );
410}
411
412 void NAFE33352_Base::dac_out( double vi, double full_scale, uint8_t bit_length )
413{
414 reg( NAFE33352_Base::Register24::AO_DATA, dac_code( vi, full_scale, bit_length ) );
415}
416
417int32_t NAFE33352_Base::dac_code( double a, double full_scale, uint8_t bit_length )
418{
419 int32_t fsv = (1L << (bit_length - 1));
420
421 int32_t v = (int32_t)((double)fsv * -a / full_scale);
422
423 v = v < -fsv ? -fsv : v;
424 v = v > (fsv - 1) ? (fsv - 1) : v;
425
426 return v << (24 - bit_length);
427}
428
429 void NAFE33352_Base::command( uint16_t com )
430{
431 write_r16( com );
432}
433
434 void NAFE33352_Base::reg( Register16 r, uint16_t value )
435{
436 write_r16( static_cast<uint16_t>( r ), value );
437}
438
439 void NAFE33352_Base::reg( Register24 r, uint32_t value )
440{
441 write_r24( static_cast<uint16_t>( r ), value );
442}
443
444uint16_t NAFE33352_Base::reg( Register16 r )
445{
446 return read_r16( static_cast<uint16_t>( r ) );
447}
448
449uint32_t NAFE33352_Base::reg( Register24 r )
450{
451 return read_r24( static_cast<uint16_t>( r ) );
452}
453
454uint64_t NAFE33352_Base::part_number( void )
455{
456 return (static_cast<uint64_t>( reg( NAFE33352_Base::Register16::PN2 ) ) << (16 + 8)) | static_cast<uint64_t>( reg( NAFE33352_Base::Register16::PN1 ) ) << 8 | reg( NAFE33352_Base::Register16::PN0_REV ) >> 8;
457}
458
459uint8_t NAFE33352_Base::revision_number( void )
460{
461 return reg( NAFE33352_Base::Register16::PN0_REV ) & 0xF;
462}
463
464uint64_t NAFE33352_Base::serial_number( void )
465{
466 uint64_t serial_number;
467
468 serial_number = reg( NAFE33352_Base::Register24::SERIAL1 );
469 serial_number <<= 24;
470 return serial_number | reg( NAFE33352_Base::Register24::SERIAL0 );
471}
472
473 float NAFE33352_Base::temperature( void )
474{
475 return ((int16_t)reg( NAFE33352_Base::Register16::DIE_TEMP )) / 64.0;
476}
477
478/* NAFE33352 class ******************************************/
479
480 NAFE33352::NAFE33352( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
481 : NAFE33352_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
482{
483}
484
485 NAFE33352::~NAFE33352()
486{
487}
488
489/* NAFE33352 class ******************************************/
490
491 NAFE33352_UIOM::NAFE33352_UIOM( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC )
492 : NAFE33352_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET, DRDY_input, SYNCDAC )
493{
494}
495
496 NAFE33352_UIOM::~NAFE33352_UIOM()
497{
498}
NAFE33352.h
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::volt_t
double volt_t
Definition AFE_NXP.h:23
AFE_base::highspeed_variant
bool highspeed_variant
Definition AFE_NXP.h:216
AFE_base::raw2uv
double raw2uv(int ch, raw_t value)
Definition AFE_NXP.h:164
AFE_base::coeff_V
double coeff_V[16]
Definition AFE_NXP.h:234
AFE_base::enabled_channels
int enabled_channels
Definition AFE_NXP.h:228
AFE_base::sequence_order
uint8_t sequence_order[16]
Definition AFE_NXP.h:231
AFE_base::AFE_base
AFE_base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition AFE_NXP.cpp:70
AFE_base::ch_delay
double ch_delay[16]
Definition AFE_NXP.h:240
AFE_base::mux_setting
int mux_setting[16]
Definition AFE_NXP.h:237
AFE_base::total_delay
double total_delay
Definition AFE_NXP.h:241
LogicalChannel_Base::LogicalChannel_Base
LogicalChannel_Base()
Definition AFE_NXP.h:264
LogicalChannel_Base::afe_ptr
AFE_base * afe_ptr
Definition AFE_NXP.h:285
LogicalChannel_Base::ch_number
int ch_number
Definition AFE_NXP.h:284
LogicalChannel_Base::disable
void disable(void)
Definition AFE_NXP.cpp:19
NAFE33352_Base::DAC
Definition NAFE33352.h:78
NAFE33352_Base::DAC::afe_ptr
NAFE33352_Base * afe_ptr
Definition NAFE33352.h:137
NAFE33352_Base::DAC::operator=
DAC & operator=(double value)
Definition NAFE33352.cpp:105
NAFE33352_Base::DAC::output_mode
ModeSelect output_mode
Definition NAFE33352.h:139
NAFE33352_Base::DAC::full_scale
double full_scale
Definition NAFE33352.h:140
NAFE33352_Base::DAC::DAC
DAC()
Definition NAFE33352.cpp:34
NAFE33352_Base::DAC::output
void output(double value)
Definition NAFE33352.cpp:100
NAFE33352_Base::DAC::~DAC
virtual ~DAC()
Definition NAFE33352.cpp:38
NAFE33352_Base::DAC::configure
void configure(const uint16_t(&cc)[6])
Definition NAFE33352.cpp:48
NAFE33352_Base::DAC::ModeSelect
ModeSelect
Definition NAFE33352.h:82
NAFE33352_Base::DAC::ModeSelect::DAC_OFF_CURRENT_IN
@ DAC_OFF_CURRENT_IN
Definition NAFE33352.h:88
NAFE33352_Base::DAC::ModeSelect::OFF
@ OFF
Definition NAFE33352.h:83
NAFE33352_Base::DAC::ModeSelect::CURRENT
@ CURRENT
Definition NAFE33352.h:85
NAFE33352_Base::DAC::ModeSelect::CURRENT_RECAL
@ CURRENT_RECAL
Definition NAFE33352.h:86
NAFE33352_Base::DAC::ModeSelect::DAC_OFF_VOLTAGE_IN
@ DAC_OFF_VOLTAGE_IN
Definition NAFE33352.h:87
NAFE33352_Base::DAC::ModeSelect::VOLTAGE
@ VOLTAGE
Definition NAFE33352.h:84
NAFE33352_Base::LogicalChannel::configure
void configure(const uint16_t(&cc)[3])
Definition NAFE33352.cpp:22
NAFE33352_Base::LogicalChannel::LogicalChannel
LogicalChannel()
Definition NAFE33352.cpp:13
NAFE33352_Base::LogicalChannel::~LogicalChannel
virtual ~LogicalChannel()
Definition NAFE33352.cpp:17
NAFE33352_Base::bit_op
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
Definition NAFE33352.h:435
NAFE33352_Base::part_number
uint64_t part_number(void)
Definition NAFE33352.cpp:454
NAFE33352_Base::revision_number
uint8_t revision_number(void)
Definition NAFE33352.cpp:459
NAFE33352_Base::read
virtual raw_t read(int ch)
Definition NAFE33352.cpp:392
NAFE33352_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition NAFE33352.cpp:349
NAFE33352_Base::Register16
Register16
Definition NAFE33352.h:254
NAFE33352_Base::Register16::CK_SRC_SEL_CONFIG
@ CK_SRC_SEL_CONFIG
Definition NAFE33352.h:268
NAFE33352_Base::Register16::SYS_CONFIG
@ SYS_CONFIG
Definition NAFE33352.h:266
NAFE33352_Base::Register16::PN1
@ PN1
Definition NAFE33352.h:274
NAFE33352_Base::Register16::AI_CONFIG2
@ AI_CONFIG2
Definition NAFE33352.h:279
NAFE33352_Base::Register16::PN0_REV
@ PN0_REV
Definition NAFE33352.h:275
NAFE33352_Base::Register16::AI_CONFIG0
@ AI_CONFIG0
Definition NAFE33352.h:277
NAFE33352_Base::Register16::SYS_STATUS
@ SYS_STATUS
Definition NAFE33352.h:267
NAFE33352_Base::Register16::AI_CONFIG1
@ AI_CONFIG1
Definition NAFE33352.h:278
NAFE33352_Base::Register16::DIE_TEMP
@ DIE_TEMP
Definition NAFE33352.h:271
NAFE33352_Base::Register16::AI_SYSCFG
@ AI_SYSCFG
Definition NAFE33352.h:281
NAFE33352_Base::Register16::PN2
@ PN2
Definition NAFE33352.h:273
NAFE33352_Base::Register16::AIO_CONFIG
@ AIO_CONFIG
Definition NAFE33352.h:286
NAFE33352_Base::Register16::AI_MULTI_CH_EN
@ AI_MULTI_CH_EN
Definition NAFE33352.h:280
NAFE33352_Base::CMD_CH0
@ CMD_CH0
Definition NAFE33352.h:364
NAFE33352_Base::CMD_MC
@ CMD_MC
Definition NAFE33352.h:378
NAFE33352_Base::CMD_AO_ABORT
@ CMD_AO_ABORT
Definition NAFE33352.h:385
NAFE33352_Base::CMD_ADC_ABORT
@ CMD_ADC_ABORT
Definition NAFE33352.h:372
NAFE33352_Base::CMD_SS
@ CMD_SS
Definition NAFE33352.h:375
NAFE33352_Base::CMD_RESET
@ CMD_RESET
Definition NAFE33352.h:357
NAFE33352_Base::CMD_MM
@ CMD_MM
Definition NAFE33352.h:377
NAFE33352_Base::boot
virtual void boot(void)
Definition NAFE33352.cpp:131
NAFE33352_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t dummy)
Definition NAFE33352.cpp:342
NAFE33352_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition NAFE33352.cpp:365
NAFE33352_Base::open_dac_output
void open_dac_output(const uint16_t(&cc)[6])
Definition NAFE33352.cpp:171
NAFE33352_Base::Register24
Register24
Definition NAFE33352.h:295
NAFE33352_Base::Register24::AI_DATA0
@ AI_DATA0
Definition NAFE33352.h:323
NAFE33352_Base::Register24::AO_DATA
@ AO_DATA
Definition NAFE33352.h:348
NAFE33352_Base::Register24::SERIAL0
@ SERIAL0
Definition NAFE33352.h:321
NAFE33352_Base::Register24::SERIAL1
@ SERIAL1
Definition NAFE33352.h:320
NAFE33352_Base::reset
virtual void reset(bool hardware_reset=false)
Definition NAFE33352.cpp:147
NAFE33352_Base::command
virtual void command(uint16_t com)
Definition NAFE33352.cpp:429
NAFE33352_Base::start
virtual void start(void)
Definition NAFE33352.cpp:377
NAFE33352_Base::~NAFE33352_Base
virtual ~NAFE33352_Base()
Definition NAFE33352.cpp:127
NAFE33352_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition NAFE33352.cpp:260
NAFE33352_Base::serial_number
uint64_t serial_number(void)
Definition NAFE33352.cpp:464
NAFE33352_Base::dac
DAC dac
Definition NAFE33352.h:143
NAFE33352_Base::dac_code
int32_t dac_code(double a, double full_scale, uint8_t bit_length)
Definition NAFE33352.cpp:417
NAFE33352_Base::NAFE33352_Base
NAFE33352_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC)
Definition NAFE33352.cpp:115
NAFE33352_Base::calc_delay
double calc_delay(int ch)
Definition NAFE33352.cpp:285
NAFE33352_Base::start_continuous_conversion
virtual void start_continuous_conversion()
Definition NAFE33352.cpp:382
NAFE33352_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition NAFE33352.h:19
NAFE33352_Base::dac_out
virtual void dac_out(double vi, double full_scale, uint8_t bit_length)
Definition NAFE33352.cpp:412
NAFE33352_Base::VCM__REF_BYP
@ VCM__REF_BYP
Definition NAFE33352.h:240
NAFE33352_Base::AIP_VSNS
@ AIP_VSNS
Definition NAFE33352.h:230
NAFE33352_Base::DAC_REF
@ DAC_REF
Definition NAFE33352.h:246
NAFE33352_Base::AIP_AIN
@ AIP_AIN
Definition NAFE33352.h:229
NAFE33352_Base::REF_BYP__VCM
@ REF_BYP__VCM
Definition NAFE33352.h:239
NAFE33352_Base::VHSS
@ VHSS
Definition NAFE33352.h:245
NAFE33352_Base::LDO
@ LDO
Definition NAFE33352.h:243
NAFE33352_Base::BG
@ BG
Definition NAFE33352.h:241
NAFE33352_Base::VCM_VCM
@ VCM_VCM
Definition NAFE33352.h:228
NAFE33352_Base::AIN
@ AIN
Definition NAFE33352.h:233
NAFE33352_Base::VCM_GPIO1
@ VCM_GPIO1
Definition NAFE33352.h:238
NAFE33352_Base::VADD
@ VADD
Definition NAFE33352.h:242
NAFE33352_Base::AIP
@ AIP
Definition NAFE33352.h:232
NAFE33352_Base::VHDD
@ VHDD
Definition NAFE33352.h:244
NAFE33352_Base::GPIO0_GPIO1
@ GPIO0_GPIO1
Definition NAFE33352.h:231
NAFE33352_Base::GPIO0_VCM
@ GPIO0_VCM
Definition NAFE33352.h:237
NAFE33352_Base::ISNS
@ ISNS
Definition NAFE33352.h:234
NAFE33352_Base::TIA
@ TIA
Definition NAFE33352.h:236
NAFE33352_Base::VSNS
@ VSNS
Definition NAFE33352.h:235
NAFE33352_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition NAFE33352.cpp:387
NAFE33352_Base::temperature
float temperature(void)
Definition NAFE33352.cpp:473
NAFE33352_Base::logical_channel
LogicalChannel logical_channel[16]
Definition NAFE33352.h:74
NAFE33352_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition NAFE33352.cpp:434
NAFE33352_UIOM::~NAFE33352_UIOM
virtual ~NAFE33352_UIOM()
Definition NAFE33352.cpp:496
NAFE33352_UIOM::NAFE33352_UIOM
NAFE33352_UIOM(bool spi_addr=0, bool highspeed_variant=false, int nINT=7, int DRDY=4, int SYN=14, int nRESET=14, int DRDY_input=2, int SYNCDAC=14)
Definition NAFE33352.cpp:491
NAFE33352::NAFE33352
NAFE33352(bool spi_addr=0, bool highspeed_variant=false, int nINT=7, int DRDY=4, int SYN=14, int nRESET=14, int DRDY_input=2, int SYNCDAC=14)
Definition NAFE33352.cpp:480
NAFE33352::~NAFE33352
virtual ~NAFE33352()
Definition NAFE33352.cpp:485
SPI_for_AFE::read_r24
int32_t read_r24(uint16_t reg)
Definition SPI_for_AFE.cpp:48
SPI_for_AFE::write_r24
void write_r24(uint16_t reg, uint32_t val)
Definition SPI_for_AFE.cpp:40
SPI_for_AFE::read_r16
uint16_t read_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:29
SPI_for_AFE::burst
void burst(uint32_t *data, int length, int width=3)
Definition SPI_for_AFE.cpp:59
SPI_for_AFE::write_r16
void write_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:13