AFE_NXP_Arduino 1.0.3 Analog Front-End (AFE) device operation sample code for Arduino

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AFE_NXP.cpp
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1
8
9#include "AFE_NXP.h"
10#include <math.h>
11
12double AFE_base::delay_accuracy = 1.2;
13
14 void LogicalChannel_Base::enable( void )
15{
16 afe_ptr->enable_logical_channel( ch_number );
17}
18
19 void LogicalChannel_Base::disable( void )
20{
21 afe_ptr->close_logical_channel( ch_number );
22}
23
24template<>
25 AFE_base::raw_t LogicalChannel_Base::read( void )
26{
27 return afe_ptr->start_and_read( ch_number );
28}
29
30template<>
31 AFE_base::microvolt_t LogicalChannel_Base::read( void )
32{
33 AFE_base::raw_t v = read<AFE_base::raw_t>();
34 return afe_ptr->raw2uv( ch_number, v );
35}
36
37LogicalChannel_Base::operator AFE_base::raw_t( void )
38{
39 return read<AFE_base::raw_t>();
40}
41
42LogicalChannel_Base::operator AFE_base::microvolt_t( void )
43{
44 return read<AFE_base::microvolt_t>();
45}
46
47NAFE13388_Base::LogicalChannel::LogicalChannel() : LogicalChannel_Base()
48{
49}
50
51NAFE13388_Base::LogicalChannel::~LogicalChannel()
52{
53 disable();
54}
55
56 void NAFE13388_Base::LogicalChannel::configure( const uint16_t (&cc)[ 4 ] )
57{
58 afe_ptr->open_logical_channel( ch_number, cc );
59}
60
61 void NAFE13388_Base::LogicalChannel::configure( uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
62{
63 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
64 afe_ptr->open_logical_channel( ch_number, tmp_ch_config );
65}
66
67
68/* AFE_base class ******************************************/
69
70AFE_base::AFE_base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input ) :
71 dev_add( spi_addr ), highspeed_variant( hsv ), pin_nINT( nINT ), pin_DRDY( DRDY ), pin_SYN( SYN ), pin_nRESET( nRESET ), pin_DRDY_input( DRDY_input ), enabled_channels( 0 )
72{
73 pinMode( pin_nINT, INPUT );
74 pinMode( pin_DRDY, INPUT );
75 pinMode( pin_DRDY_input,INPUT_PULLUP );
76 pinMode( pin_SYN, OUTPUT );
77 pinMode( pin_nRESET, OUTPUT );
78
79 digitalWrite( pin_SYN, 1 );
80 digitalWrite( pin_nRESET, 1 );
81}
82
83AFE_base::~AFE_base()
84{
85}
86
87 void AFE_base::init( void )
88{
89 attachInterrupt( digitalPinToInterrupt( pin_DRDY_input ), DRDY_cb, CHANGE );
90
91 drdy_flag = false;
92 set_DRDY_callback( static_default_drdy_cb );
93
94 use_DRDY_trigger( false );
95}
96
97 void AFE_base::begin( void )
98{
99 instance = this;
100
101 reset();
102 boot();
103 init();
104}
105
106 void AFE_base::set_DRDY_callback( callback_fp_t func )
107{
108 cbf_DRDY = func;
109}
110
111 void AFE_base::DRDY_cb( void )
112{
113 if ( cbf_DRDY )
114 cbf_DRDY();
115}
116
117 void AFE_base::static_default_drdy_cb( void )
118{
119 if ( nullptr != instance )
120 instance->default_drdy_cb();
121}
122
123 void AFE_base::default_drdy_cb( void )
124{
125 drdy_count++;
126 drdy_flag = true;
127}
128
129int32_t AFE_base::start_and_read( int ch )
130{
131 double wait_time = cbf_DRDY ? -1.0 : ch_delay[ ch ] * delay_accuracy;
132
133 start( ch );
134 wait_conversion_complete( wait_time );
135
136 return read( ch );
137};
138
139#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
140void AFE_base::start_and_read( raw_t* data )
141{
142 double wait_time = cbf_DRDY ? -1.0 : total_delay * delay_accuracy;
143
144 start();
145 wait_conversion_complete( wait_time );
146
147 read( data );
148};
149template void AFE_base::start_and_read( raw_t* data );
150#endif
151
152 int AFE_base::bit_count( uint32_t value )
153{
154 constexpr int bit_length = 32;
155 int count = 0;
156
157 for ( int i = 0; i < bit_length; i++ ) {
158 if ( value & (0x1 << i) )
159 count++;
160 }
161
162 return count;
163}
164
165 int AFE_base::wait_conversion_complete( double wait )
166{
167 if ( 0 < wait )
168 {
169 delay( wait * delay_accuracy * 1000 );
170 return 0;
171 }
172
173 auto timeout_count = timeout_limit;
174
175 while ( !drdy_flag && --timeout_count )
176 ;
177
178 drdy_flag = false;
179
180 if ( !timeout_count )
181 {
182 printf( "DRDY signal wait timeout\r\n" );
183 return -1;
184 }
185 return 0;
186}
187
188 void AFE_base::use_DRDY_trigger( bool use )
189{
190 if ( use )
191 set_DRDY_callback( static_default_drdy_cb );
192 else
193 set_DRDY_callback( nullptr );
194}
195
196
197 AFE_base* AFE_base::instance = nullptr;
198 AFE_base::callback_fp_t AFE_base::cbf_DRDY = nullptr;
199
200/* NAFE13388_Base class ******************************************/
201
202NAFE13388_Base::NAFE13388_Base( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET )
203 : AFE_base( spi_addr, hsv, nINT, DRDY, SYN, nRESET )
204{
205 for ( auto i = 0; i < 16; i++ )
206 {
207 logical_channel[ i ].afe_ptr = this;
208 logical_channel[ i ].ch_number = i;
209 }
210}
211
212NAFE13388_Base::~NAFE13388_Base()
213{
214}
215
216 void NAFE13388_Base::boot( void )
217{
218 command( CMD_ABORT );
219 delay( 1 );
220
221 DRDY_by_sequencer_done( true );
222}
223
224 void NAFE13388_Base::reset( bool hardware_reset )
225{
226 if ( hardware_reset )
227 {
228 digitalWrite( pin_nRESET, 0 );
229 delay( 1 );
230 digitalWrite( pin_nRESET, 1 );
231 }
232 else
233 {
234 command( CMD_RESET );
235 }
236
237 constexpr uint16_t CHIP_READY = 1 << 13;
238 constexpr auto RETRY = 10;
239
240 for ( auto i = 0; i < RETRY; i++ )
241 {
242 delay( 3 );
243 if ( reg( Register16::SYS_STATUS0 ) & CHIP_READY )
244 return;
245 }
246
247 Serial.println( "NAFE13388 couldn't get ready. Check power supply or pin conections\r\n" );
248
249 while ( true )
250 ;
251}
252
253 void NAFE13388_Base::open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] )
254{
255 command( ch );
256
257 if ( cc[ 0 ] & 0x0010 )
258 {
259 coeff_uV[ ch ] = ((10.0 / (double)(1L << 24)) / pga_gain[ (cc[ 0 ] >> 5) & 0x7 ]) * 1e6;
260 mux_setting[ ch ] = HV_MUX;
261 }
262 else
263 {
264 coeff_uV[ ch ] = ((10.0 / (double)(1L << 24)) / 2.5) * 1e6;
265 mux_setting[ ch ] = (cc[ 0 ] >> 1) & 0x7;
266 }
267
268 for ( auto i = 0; i < 4; i++ )
269 reg( Register16::CH_CONFIG0 + i, cc[ i ] );
270
271 enable_logical_channel( ch );
272
273 ch_delay[ ch ] = calc_delay( ch );
274}
275
276 void NAFE13388_Base::channel_info_update( uint16_t value )
277{
278 constexpr auto bit_length = 16;
279 enabled_channels = 0;
280 total_delay = 0.00;
281
282 memset( sequence_order, 0, 16 );
283
284 for ( auto i = 0; i < bit_length; i++ )
285 {
286 if ( value & (0x1 << i) )
287 {
288 sequence_order[ enabled_channels ] = i;
289 enabled_channels++;
290 total_delay += ch_delay[ i ];
291 }
292 }
293
294#if 0
295 for ( auto i = 0; i < bit_length; i++ )
296 printf( " %x", sequence_order[ i ] );
297 printf( "\r\n" );
298#endif
299}
300
301 double NAFE13388_Base::calc_delay( int ch )
302{
303 constexpr static double data_rates[] = { 288000, 192000, 144000, 96000, 72000, 48000, 36000, 24000,
304 18000, 12000, 9000, 6000, 4500, 3000, 2250, 1125,
305 562.5, 400, 300, 200, 100, 60, 50, 30,
306 25, 20, 15, 10, 7.5, };
307 constexpr static uint16_t delays[] = { 0, 2, 4, 6, 8, 10, 12, 14,
308 16, 18, 20, 28, 38, 40, 42, 56,
309 64, 76, 90, 128, 154, 178, 204, 224,
310 256, 358, 512, 716,
311 1024, 1664, 3276, 7680, 19200, 23040, };
312
313 command( ch );
314
315 uint16_t ch_config1 = reg( Register16::CH_CONFIG1 );
316 uint16_t ch_config2 = reg( Register16::CH_CONFIG2 );
317
318 uint8_t adc_data_rate = (ch_config1 >> 3) & 0x001F;
319 uint8_t adc_sinc = (ch_config1 >> 0) & 0x0007;
320 uint8_t ch_delay = (ch_config2 >> 10) & 0x003F;
321 bool adc_normal_setting = (ch_config2 >> 9) & 0x0001;
322 bool ch_chop = (ch_config2 >> 7) & 0x0001;
323
324 double base_freq = data_rates[ adc_data_rate ];
325 double delay_setting = delays[ ch_delay ] / 4608000.00;
326
327 if ( highspeed_variant )
328 {
329 base_freq *= 2.00;
330 delay_setting /= 2.00;
331 }
332
333 if ( (28 < adc_data_rate) || (4 < adc_sinc) || ((adc_data_rate < 12) && (adc_sinc)) )
334 return 0.00;
335
336 if ( !adc_normal_setting )
337 base_freq /= (adc_sinc + 1);
338
339 if ( ch_chop )
340 base_freq /= 2;
341
342#if 0
343 printf( "base_freq = %lf\r\n", base_freq );
344 printf( "delay_setting = %lf\r\n", delay_setting );
345 printf( "total delay = %lf\r\n", (1 / base_freq) + delay_setting );
346#endif
347
348 return (1 / base_freq) + delay_setting;
349}
350
351 void NAFE13388_Base::open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 )
352{
353 const ch_setting_t tmp_ch_config = { cc0, cc1, cc2, cc3 };
354 open_logical_channel( ch, tmp_ch_config );
355}
356
357 void NAFE13388_Base::enable_logical_channel( int ch )
358{
359 const uint16_t setbit = 0x1 << ch;
360 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~setbit, setbit );
361
362 channel_info_update( bits );
363}
364
365 void NAFE13388_Base::close_logical_channel( int ch )
366{
367 const uint16_t clearingbit = 0x1 << ch;
368 const uint16_t bits = bit_op( Register16::CH_CONFIG4, ~clearingbit, ~clearingbit );
369
370 channel_info_update( bits );
371}
372
373 void NAFE13388_Base::close_logical_channel( void )
374{
375 reg( Register16::CH_CONFIG4, 0x0000 );
376 channel_info_update( 0x0000 );
377}
378
379 void NAFE13388_Base::start( int ch )
380{
381 command( ch );
382 command( Command::CMD_SS );
383}
384
385 void NAFE13388_Base::start( void )
386{
387 command( Command::CMD_MM );
388}
389
390 void NAFE13388_Base::start_continuous_conversion( void )
391{
392 command( Command::CMD_MC );
393}
394
395 void NAFE13388_Base::DRDY_by_sequencer_done( bool flag )
396{
397 bit_op( Register16::SYS_CONFIG0, ~0x0010, flag ? 0x0010 : 0x00 );
398}
399
400int32_t NAFE13388_Base::read( int ch )
401{
402 return reg( Register24::CH_DATA0 + ch );
403}
404
405 void NAFE13388_Base::read( raw_t *data )
406{
407 burst( (uint32_t *)data, enabled_channels );
408}
409
410 void NAFE13388_Base::read( microvolt_t *data )
411{
412 raw_t raw_data[ 16 ];
413
414 read( raw_data );
415
416 for ( auto i = 0; i < enabled_channels; i++ )
417 data[ i ] = raw2uv( sequence_order[ i ], raw_data[ i ] );
418}
419
420 void NAFE13388_Base::command( uint16_t com )
421{
422 write_r16( com );
423}
424
425 void NAFE13388_Base::reg( Register16 r, uint16_t value )
426{
427 write_r16( static_cast<uint16_t>( r ), value );
428}
429
430 void NAFE13388_Base::reg( Register24 r, uint32_t value )
431{
432 write_r24( static_cast<uint16_t>( r ), value );
433}
434
435uint16_t NAFE13388_Base::reg( Register16 r )
436{
437 return read_r16( static_cast<uint16_t>( r ) );
438}
439
440uint32_t NAFE13388_Base::reg( Register24 r )
441{
442 return read_r24( static_cast<uint16_t>( r ) );
443}
444
445uint32_t NAFE13388_Base::part_number( void )
446{
447 return (static_cast<uint32_t>( reg( Register16::PN2 ) ) << 16) | reg( Register16::PN1 );
448}
449
450uint8_t NAFE13388_Base::revision_number( void )
451{
452 return reg( Register16::PN0 ) & 0xF;
453}
454
455uint64_t NAFE13388_Base::serial_number( void )
456{
457 uint64_t serial_number;
458
459 serial_number = reg( Register24::SERIAL1 );
460 serial_number <<= 24;
461 return serial_number | reg( Register24::SERIAL0 );
462}
463
464 float NAFE13388_Base::temperature( void )
465{
466 return reg( Register16::DIE_TEMP ) / 64.0;
467}
468
469 void NAFE13388_Base::gain_offset_coeff( const ref_points &ref )
470{
471 constexpr double pga1x_voltage = 5.0;
472 constexpr int adc_resolution = 24;
473 constexpr double pga_gain_setting = 0.2;
474
475 constexpr double fullscale_voltage = pga1x_voltage / pga_gain_setting;
476
477 double fullscale_data = pow( 2, (adc_resolution - 1) );
478 double ref_data_span = ref.high.data - ref.low.data;
479 double ref_voltage_span = ref.high.voltage - ref.low.voltage;
480
481 double dv_slope = ref_data_span / ref_voltage_span;
482 double custom_gain = dv_slope * (fullscale_voltage / fullscale_data);
483 double custom_offset = (dv_slope * ref.low.voltage - ref.low.data) / custom_gain;
484
485 int32_t gain_coeff_cal = reg( Register24::GAIN_COEFF0 + ref.cal_index );
486 int32_t offsset_coeff_cal = reg( Register24::OFFSET_COEFF0 + ref.cal_index );
487 int32_t gain_coeff_new = round( gain_coeff_cal * custom_gain );
488 int32_t offset_coeff_new = round( custom_offset - offsset_coeff_cal );
489
490#if 0
491 printf( "ref_point_high = %8ld @%6.3lf\r\n", ref.high.data, ref.high.voltage );
492 printf( "ref_point_low = %8ld @%6.3lf\r\n", ref.low.data, ref.low.voltage );
493 printf( "gain_coeff_new = %8ld\r\n", gain_coeff_new );
494 printf( "offset_coeff_new = %8ld\r\n", offset_coeff_new );
495#endif
496
497 reg( Register24::GAIN_COEFF0 + ref.coeff_index, gain_coeff_new );
498 reg( Register24::OFFSET_COEFF0 + ref.coeff_index, offset_coeff_new );
499}
500
501 int NAFE13388_Base::self_calibrate( int pga_gain_index, int channel_selection, int input_select, double reference_source_voltage, bool use_positive_side )
502{
503 constexpr auto low_gain_index = 2;
504 auto channel_in_use = false;
505 ch_setting_t tmp_ch_config;
506 int gain_index = static_cast<int>( pga_gain_index );
507
508 // logical channel selection to perform the self-calibration
509 // if the chennel in-use, save channel setting to temporal memory
510
511 if ( reg( Register16::CH_CONFIG4 ) & (0x1 << channel_selection) )
512 {
513 channel_in_use = true;
514
515 command( channel_selection );
516
517 for ( auto i = 0; i < 4; i++ )
518 tmp_ch_config[ i ] = reg( Register16::CH_CONFIG0 + i );
519 }
520
521 // if user doesn't specify the channel and voltage, use REFH or REFL
522
523 if ( !input_select )
524 {
525 bool low_gain = (gain_index <= low_gain_index);
526
527 input_select = low_gain ? 0x5 : 0x6;
528 reference_source_voltage = (reg( low_gain ? Register24::OPT_COEF1 : Register24::OPT_COEF2 ) * 5.00) / (double)(1UL << 24);
529
530#if 1
531 printf( "==== self-calibration for PGA gain setting: x%3.1lf\r\n", pga_gain[ gain_index ] );
532 printf( "gain = %s\r\n", low_gain ? "low" : "high" );
533 printf( "REF%s = %10.8lfV\r\n", low_gain ? "H" : "L", reference_source_voltage );
534#endif
535 }
536
537 // logical channel settings
538 // Total 3 settings are prepared to measure reference_voltage, internal-GND and AICOM
539
540 const uint16_t REF_GND = 0x0011 | (gain_index << 5);
541 const uint16_t REF_V = (input_select << (use_positive_side ? 12 : 8)) | REF_GND;
542 const uint16_t REF_COM = 0x7700 | REF_GND;
543 const uint16_t ch_config1 = (gain_index << 12) | 0x00E4;
544 constexpr uint16_t ch_config2 = 0x8480;
545 constexpr uint16_t ch_config3 = 0x0000;
546
547 const ch_setting_t refh = { REF_V, ch_config1, ch_config2, ch_config3 };
548 const ch_setting_t refg = { REF_GND, ch_config1, ch_config2, ch_config3 };
549 const ch_setting_t refc = { REF_COM, ch_config1, ch_config2 & ~0x0080, ch_config3 }; //CH_CHOP:off
550
551 // forcing to set unity-gain and zero-offset
552
553 constexpr raw_t default_gain_coeff_value = 0x1UL << 22;
554 constexpr raw_t default_offset_coeff_value = 0;
555
556 reg( Register24::GAIN_COEFF0 + gain_index, default_gain_coeff_value );
557 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value );
558
559 // measure the logical channel with those different 3 settings
560
561 open_logical_channel( channel_selection, refh );
562 raw_t data_REF = start_and_read( channel_selection );
563
564 open_logical_channel( channel_selection, refg );
565 raw_t data_GND = start_and_read( channel_selection );
566
567 open_logical_channel( channel_selection, refc );
568 raw_t data_COM = start_and_read( channel_selection );
569
570 // calculation
571
572 const double fullscale_voltage = 5.00 / pga_gain[ gain_index ];
573 const double calibrated_gain = (double)(0x1UL << 23) * (reference_source_voltage / fullscale_voltage) / (double)(data_REF - data_GND);
574
575#if 0
576 printf( "data_REF = %8ld (%lfV)\r\n", data_REF, raw2v( channel_selection, data_REF ) );
577 printf( "data_GND = %8ld (%lfmV)\r\n", data_GND, raw2mv( channel_selection, data_GND ) );
578 printf( "data_COM = %8ld (%lfmV)\r\n", data_COM, raw2mv( channel_selection, data_COM ) );
579 printf( "gain adjustment = %8lf (%lfdB)\r\n\r\n", calibrated_gain, 20 * log10( calibrated_gain ) );
580#endif
581
582 if ( !( (0.95 < calibrated_gain) && (calibrated_gain < 1.05) ) )
583 return CalibrationError::GainError;
584
585 const double offset_mv = raw2mv( channel_selection, data_COM );
586
587 if ( !( (-10.0 < offset_mv) && (offset_mv < 10.0) ) )
588 return CalibrationError::OffsetError;
589
590 // setting registers: GAIN_COEFF[n] and OFFSET_COEFF[n]
591
592 reg( Register24::GAIN_COEFF0 + gain_index, (uint32_t)(default_gain_coeff_value * calibrated_gain) );
593 reg( Register24::OFFSET_COEFF0 + gain_index, default_offset_coeff_value + data_COM );
594
595 // if the channel was in-use, revert the setting
596
597 if ( channel_in_use )
598 open_logical_channel( channel_selection, tmp_ch_config );
599 else
600 close_logical_channel( channel_selection );
601
602 return CalibrationError::NoError;
603}
604
605 void NAFE13388_Base::blink_leds( void )
606{
607}
608
609
610/* NAFE13388 class ******************************************/
611
612NAFE13388::NAFE13388( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET )
613 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET )
614{
615}
616
617NAFE13388::~NAFE13388()
618{
619}
620
621/* NAFE13388_UIM class ******************************************/
622
623NAFE13388_UIM::NAFE13388_UIM( bool spi_addr, bool hsv, int nINT, int DRDY, int SYN, int nRESET )
624 : NAFE13388_Base( spi_addr, hsv, nINT, DRDY, SYN, nRESET )
625{
626}
627
628NAFE13388_UIM::~NAFE13388_UIM()
629{
630}
631
632 void NAFE13388_UIM::blink_leds( void )
633{
634 uint16_t pattern[] = {
635 0x8000, 0x0040, 0x0100, 0x0080, 0x0200, 0x0400, 0x0800, 0x1000,
636 0x2000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0080,
637 0x0100, 0x0040,
638 };
639 reg( Register16::GPIO_CONFIG0, 0xFFC0 );
640 reg( Register16::GPIO_CONFIG1, 0xFFC0 );
641 reg( Register16::GPIO_CONFIG2, 0x0000 );
642
643 for ( auto j = 0; j < 2; j++ )
644 {
645 for ( auto i = 0U; i < sizeof( pattern ) / sizeof( uint16_t ); i++ )
646 {
647 reg( Register16::GPO_DATA, pattern[ i ] );
648 delay( 20 );
649 }
650 }
651
652 uint16_t pv = 0;
653
654 for ( auto j = 0; j < 4; j++ )
655 {
656 for ( auto i = 0; i < 10; i++ )
657 {
658 pv = (j % 2) ? pv & ~pattern[ i ] : pv | pattern[ i ];
659 reg( Register16::GPO_DATA, pv ); delay( 20 );
660 }
661 }
662}
663
664double NAFE13388_Base::pga_gain[] = { 0.2, 0.4, 0.8, 1, 2, 4, 8, 16 };
665
AFE_NXP.h
AFE_base
Definition AFE_NXP.h:18
AFE_base::instance
static AFE_base * instance
Definition AFE_NXP.h:295
AFE_base::cbf_DRDY
static callback_fp_t cbf_DRDY
Definition AFE_NXP.h:287
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::AFE_base
AFE_base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input=2)
Definition AFE_NXP.cpp:70
AFE_base::microvolt_t
double microvolt_t
Definition AFE_NXP.h:23
AFE_base::use_DRDY_trigger
void use_DRDY_trigger(bool use=true)
Definition AFE_NXP.cpp:188
AFE_base::~AFE_base
virtual ~AFE_base()
Definition AFE_NXP.cpp:83
AFE_base::DRDY_cb
static void DRDY_cb()
Definition AFE_NXP.cpp:111
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Definition AFE_NXP.h:256
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Definition AFE_NXP.cpp:106
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Definition AFE_NXP.h:260
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Definition AFE_NXP.cpp:87
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Definition AFE_NXP.h:281
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Definition AFE_NXP.cpp:97
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Definition AFE_NXP.h:201
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Definition AFE_NXP.h:156
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Definition AFE_NXP.h:255
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Definition AFE_NXP.h:285
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Definition AFE_NXP.cpp:152
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Definition AFE_NXP.h:271
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Definition AFE_NXP.cpp:123
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Definition AFE_NXP.h:164
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Definition AFE_NXP.h:46
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Definition AFE_NXP.cpp:129
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Definition AFE_NXP.h:265
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Definition AFE_NXP.h:268
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Definition AFE_NXP.cpp:117
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Definition AFE_NXP.cpp:165
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Definition AFE_NXP.h:286
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Definition AFE_NXP.h:258
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Definition AFE_NXP.h:279
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Definition AFE_NXP.h:277
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Definition AFE_NXP.h:274
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Definition AFE_NXP.h:259
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Definition AFE_NXP.h:254
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Definition AFE_NXP.h:211
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Definition AFE_NXP.h:257
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Definition AFE_NXP.h:278
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Definition AFE_NXP.h:301
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Definition AFE_NXP.cpp:14
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Definition AFE_NXP.h:322
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Definition AFE_NXP.h:321
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Definition AFE_NXP.cpp:19
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Definition AFE_NXP.cpp:51
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Definition AFE_NXP.cpp:47
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Definition AFE_NXP.cpp:56
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Definition AFE_NXP.cpp:390
NAFE13388_Base::NAFE13388_Base
NAFE13388_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET)
Definition AFE_NXP.cpp:202
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Definition AFE_NXP.cpp:216
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Definition AFE_NXP.cpp:469
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Definition AFE_NXP.cpp:301
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Definition AFE_NXP.cpp:420
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Definition AFE_NXP.cpp:605
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virtual raw_t read(int ch)
Definition AFE_NXP.cpp:400
NAFE13388_Base::logical_channel
LogicalChannel logical_channel[16]
Definition AFE_NXP.h:381
NAFE13388_Base::pga_gain
static double pga_gain[]
Definition AFE_NXP.h:664
NAFE13388_Base::bit_op
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
Definition AFE_NXP.h:664
NAFE13388_Base::self_calibrate
int self_calibrate(int pga_gain_index, int channel_selection=15, int input_select=0, double reference_source_voltage=0, bool use_positive_side=true)
Definition AFE_NXP.cpp:501
NAFE13388_Base::ref_points
struct NAFE13388_Base::_ref_points ref_points
NAFE13388_Base::start
virtual void start(void)
Definition AFE_NXP.cpp:385
NAFE13388_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition AFE_NXP.cpp:425
NAFE13388_Base::revision_number
uint8_t revision_number(void)
Definition AFE_NXP.cpp:450
NAFE13388_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition AFE_NXP.cpp:373
NAFE13388_Base::Register24
Register24
Definition AFE_NXP.h:486
NAFE13388_Base::Register24::OFFSET_COEFF0
@ OFFSET_COEFF0
Definition AFE_NXP.h:550
NAFE13388_Base::Register24::GAIN_COEFF0
@ GAIN_COEFF0
Definition AFE_NXP.h:534
NAFE13388_Base::Register24::OPT_COEF2
@ OPT_COEF2
Definition AFE_NXP.h:568
NAFE13388_Base::Register24::SERIAL0
@ SERIAL0
Definition AFE_NXP.h:581
NAFE13388_Base::Register24::OPT_COEF1
@ OPT_COEF1
Definition AFE_NXP.h:567
NAFE13388_Base::Register24::SERIAL1
@ SERIAL1
Definition AFE_NXP.h:580
NAFE13388_Base::Register24::CH_DATA0
@ CH_DATA0
Definition AFE_NXP.h:487
NAFE13388_Base::CMD_MM
@ CMD_MM
Definition AFE_NXP.h:611
NAFE13388_Base::CMD_MC
@ CMD_MC
Definition AFE_NXP.h:612
NAFE13388_Base::CMD_SS
@ CMD_SS
Definition AFE_NXP.h:609
NAFE13388_Base::CMD_RESET
@ CMD_RESET
Definition AFE_NXP.h:605
NAFE13388_Base::CMD_ABORT
@ CMD_ABORT
Definition AFE_NXP.h:601
NAFE13388_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition AFE_NXP.cpp:395
NAFE13388_Base::serial_number
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Definition AFE_NXP.cpp:455
NAFE13388_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition AFE_NXP.cpp:276
NAFE13388_Base::~NAFE13388_Base
virtual ~NAFE13388_Base()
Definition AFE_NXP.cpp:212
NAFE13388_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition AFE_NXP.cpp:357
NAFE13388_Base::reset
virtual void reset(bool hardware_reset=false)
Definition AFE_NXP.cpp:224
NAFE13388_Base::part_number
uint32_t part_number(void)
Definition AFE_NXP.cpp:445
NAFE13388_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
Definition AFE_NXP.cpp:351
NAFE13388_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition AFE_NXP.h:328
NAFE13388_Base::Register16
Register16
Definition AFE_NXP.h:456
NAFE13388_Base::Register16::CH_CONFIG1
@ CH_CONFIG1
Definition AFE_NXP.h:458
NAFE13388_Base::Register16::CH_CONFIG2
@ CH_CONFIG2
Definition AFE_NXP.h:459
NAFE13388_Base::Register16::GPIO_CONFIG0
@ GPIO_CONFIG0
Definition AFE_NXP.h:466
NAFE13388_Base::Register16::PN1
@ PN1
Definition AFE_NXP.h:481
NAFE13388_Base::Register16::CH_CONFIG4
@ CH_CONFIG4
Definition AFE_NXP.h:461
NAFE13388_Base::Register16::SYS_STATUS0
@ SYS_STATUS0
Definition AFE_NXP.h:473
NAFE13388_Base::Register16::PN0
@ PN0
Definition AFE_NXP.h:482
NAFE13388_Base::Register16::GPIO_CONFIG2
@ GPIO_CONFIG2
Definition AFE_NXP.h:468
NAFE13388_Base::Register16::DIE_TEMP
@ DIE_TEMP
Definition AFE_NXP.h:476
NAFE13388_Base::Register16::CH_CONFIG0
@ CH_CONFIG0
Definition AFE_NXP.h:457
NAFE13388_Base::Register16::GPIO_CONFIG1
@ GPIO_CONFIG1
Definition AFE_NXP.h:467
NAFE13388_Base::Register16::GPO_DATA
@ GPO_DATA
Definition AFE_NXP.h:471
NAFE13388_Base::Register16::PN2
@ PN2
Definition AFE_NXP.h:480
NAFE13388_Base::Register16::SYS_CONFIG0
@ SYS_CONFIG0
Definition AFE_NXP.h:472
NAFE13388_Base::temperature
float temperature(void)
Definition AFE_NXP.cpp:464
NAFE13388_Base::NoError
@ NoError
Definition AFE_NXP.h:708
NAFE13388_Base::OffsetError
@ OffsetError
Definition AFE_NXP.h:710
NAFE13388_Base::GainError
@ GainError
Definition AFE_NXP.h:709
NAFE13388_UIM::NAFE13388_UIM
NAFE13388_UIM(bool spi_addr=0, bool highspeed_variant=false, int nINT=3, int DRDY=3, int SYN=6, int nRESET=7)
Definition AFE_NXP.cpp:623
NAFE13388_UIM::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:632
NAFE13388_UIM::~NAFE13388_UIM
virtual ~NAFE13388_UIM()
Definition AFE_NXP.cpp:628
NAFE13388::~NAFE13388
virtual ~NAFE13388()
Definition AFE_NXP.cpp:617
NAFE13388::NAFE13388
NAFE13388(bool spi_addr=0, bool highspeed_variant=false, int nINT=2, int DRDY=3, int SYN=5, int nRESET=6)
Definition AFE_NXP.cpp:612
SPI_for_AFE::read_r24
int32_t read_r24(uint16_t reg)
Definition SPI_for_AFE.cpp:48
SPI_for_AFE::write_r24
void write_r24(uint16_t reg, uint32_t val)
Definition SPI_for_AFE.cpp:40
SPI_for_AFE::read_r16
uint16_t read_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:29
SPI_for_AFE::burst
void burst(uint32_t *data, int length, int width=3)
Definition SPI_for_AFE.cpp:59
SPI_for_AFE::write_r16
void write_r16(uint16_t reg)
Definition SPI_for_AFE.cpp:13
NAFE13388_Base::_ref_points::coeff_index
int coeff_index
Definition AFE_NXP.h:336
NAFE13388_Base::_ref_points::high
reference_point high
Definition AFE_NXP.h:337
NAFE13388_Base::_ref_points::low
reference_point low
Definition AFE_NXP.h:338
NAFE13388_Base::_ref_points::cal_index
int cal_index
Definition AFE_NXP.h:339
NAFE13388_Base::_reference_point::voltage
double voltage
Definition AFE_NXP.h:331
NAFE13388_Base::_reference_point::data
int32_t data
Definition AFE_NXP.h:332