AFE_NXP_Arduino 1.0.3 Analog Front-End (AFE) device operation sample code for Arduino

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AFE_NXP.h
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1
8
9#ifndef ARDUINO_AFE_DRIVER_H
10#define ARDUINO_AFE_DRIVER_H
11
12#include <Arduino.h>
13#include <math.h>
14#include <stdint.h>
15#include <SPI_for_AFE.h>
16
17 class AFE_base : public SPI_for_AFE
18{
19public:
20
22 using raw_t = int32_t;
23 using microvolt_t = double;
24
26 AFE_base( bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input = 2 );
27
29 virtual ~AFE_base();
30
37 virtual void begin( void );
38
40 virtual void boot( void ) = 0;
41
43 virtual void reset( bool hardware_reset = false ) = 0;
44
46 typedef void (*callback_fp_t)( void );
47 virtual void set_DRDY_callback( callback_fp_t fnc );
48
50
59 virtual void open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 ) = 0;
60
66 virtual void open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] ) = 0;
67
72 virtual void close_logical_channel( int ch ) = 0;
73
76 virtual void close_logical_channel( void ) = 0;
77
82 virtual void enable_logical_channel( int ch ) = 0;
83
88 virtual void start( int ch ) = 0;
89
92 virtual void start( void ) = 0;
93
96 virtual void start_continuous_conversion( void ) = 0;
97
102 virtual void DRDY_by_sequencer_done( bool flag = true ) = 0;
103
108 virtual raw_t read( int ch ) = 0;
109
114 virtual void read( raw_t *data_ptr ) = 0;
115
120 virtual void read( microvolt_t *data_ptr ) = 0;
121
126 virtual raw_t start_and_read( int ch );
127
128#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
129
134 virtual void start_and_read( raw_t *data_ptr );
135
136#else
137 template<typename T>
138 inline void start_and_read( T data )
139 {
140 double wait_time = cbf_DRDY ? -1.0 : total_delay * delay_accuracy;
141
142 start();
143 wait_conversion_complete( wait_time );
144
145 read( data );
146 };
147#endif
148
149 enum LV_mux_sel : uint8_t {
150 REF2_REF2 = 0,
151 GPIO0_GPIO1,
152 REFCOARSE_REF2,
153 VADD_REF2,
154 VHDD_REF2,
155 REF2_VHSS,
156 HV_MUX,
157 };
158
164 inline double raw2uv( int ch, raw_t value )
165 {
166 double v = value * coeff_uV[ ch ];
167
168 if ( HV_MUX != mux_setting[ ch ] )
169 {
170#if 1
171 switch ( mux_setting[ ch ] )
172 {
173 case REF2_REF2:
174 case GPIO0_GPIO1:
175 return v;
176 break;
177 case REFCOARSE_REF2:
178 case VADD_REF2:
179 return 2.00 * (v + 1.5e6);
180 break;
181 case VHDD_REF2:
182 return 32.00 * (v + 0.25e6);
183 break;
184 case REF2_VHSS:
185 return -32.00 * (v - 0.25e6);
186 break;
187 }
188#else
189 return v;
190#endif
191 }
192
193 return v;
194 }
195
201 inline double raw2mv( int ch, raw_t value )
202 {
203 return value * coeff_uV[ ch ] * 1e-3;
204 }
205
211 inline double raw2v( int ch, raw_t value )
212 {
213 return value * coeff_uV[ ch ] * 1e-6;
214 }
215
220 inline double coeff_mV( int ch )
221 {
222 return coeff_uV[ ch ];
223 }
224
229 inline double drdy_delay( int ch )
230 {
231 return ch_delay[ ch ];
232 }
233
236 inline double drdy_delay( void )
237 {
238 return total_delay;
239 }
240
242 inline int enabled_logical_channels( void )
243 {
244 return enabled_channels;
245 }
246
251 void use_DRDY_trigger( bool use = true );
252
253protected:
254 bool dev_add;
255 bool highspeed_variant;
256 int pin_nINT;
257 int pin_DRDY;
258 int pin_SYN;
259 int pin_nRESET;
260 int pin_DRDY_input;
261
262 int bit_count( uint32_t value );
263
265 int enabled_channels;
266
268 uint8_t sequence_order[ 16 ];
269
271 double coeff_uV[ 16 ];
272
274 int mux_setting[ 16 ];
275
277 double ch_delay[ 16 ];
278 double total_delay;
279 static double delay_accuracy;
280
281 constexpr static uint32_t timeout_limit = 10000000;
282
283 void default_drdy_cb();
284 static void static_default_drdy_cb();
285 uint32_t drdy_count;
286 volatile bool drdy_flag;
287 static callback_fp_t cbf_DRDY;
288 static void DRDY_cb();
289
290 virtual void init( void );
291
292 int wait_conversion_complete( double delay = -1.0 );
293
294public:
295 static AFE_base* instance;
296};
297
298 class LogicalChannel_Base
299{
300public:
301 LogicalChannel_Base() {}
302 virtual ~LogicalChannel_Base() {}
303
304 void enable( void );
305 void disable( void );
306
307 template<class T> T read(void);
308
309 operator AFE_base::raw_t(void);
310 operator AFE_base::microvolt_t(void);
311
312 template<class T> double operator+( T v ) { return (double)(*this) + (double)v; }
313 template<class T> double operator-( T v ) { return (double)(*this) - (double)v; }
314 template<class T> double operator*( T v ) { return (double)(*this) * (double)v; }
315 template<class T> double operator/( T v ) { return (double)(*this) / (double)v; }
316 template<class T> friend double operator+( T v, LogicalChannel_Base lc ) { return (double)v + (double)lc; }
317 template<class T> friend double operator-( T v, LogicalChannel_Base lc ) { return (double)v - (double)lc; }
318 template<class T> friend double operator*( T v, LogicalChannel_Base lc ) { return (double)v * (double)lc; }
319 template<class T> friend double operator/( T v, LogicalChannel_Base lc ) { return (double)v / (double)lc; }
320
321 int ch_number;
322 AFE_base *afe_ptr;
323};
324
325 class NAFE13388_Base : public AFE_base
326{
327public:
328 using ch_setting_t = uint16_t[ 4 ];
329
330 typedef struct _reference_point {
331 double voltage;
332 int32_t data;
333 } reference_point;
334
335 typedef struct _ref_points {
336 int coeff_index;
337 reference_point high;
338 reference_point low;
339 int cal_index;
340 } ref_points;
341
343 NAFE13388_Base( bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET );
344
346 virtual ~NAFE13388_Base();
347
349 virtual void boot( void );
350
352 virtual void reset( bool hardware_reset = false );
353
362 virtual void open_logical_channel( int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 );
363
369 virtual void open_logical_channel( int ch, const uint16_t (&cc)[ 4 ] );
370
371 class LogicalChannel : public LogicalChannel_Base
372 {
373 public:
374 LogicalChannel();
375 virtual ~LogicalChannel();
376
377 void configure( const uint16_t (&cc)[ 4 ] );
378 void configure( uint16_t cc0 = 0x0000, uint16_t cc1 = 0x0000, uint16_t cc2 = 0x0000, uint16_t cc3 = 0x0000 );
379 };
380
381 LogicalChannel logical_channel[ 16 ];
382
383 private:
384 double calc_delay( int ch );
385 void channel_info_update( uint16_t value );
386
387public:
392 virtual void close_logical_channel( int ch );
393
396 virtual void close_logical_channel( void );
397
402 void enable_logical_channel( int ch );
403
408 virtual void start( int ch );
409
412 virtual void start( void );
413
416 virtual void start_continuous_conversion();
417
422 virtual void DRDY_by_sequencer_done( bool flag = true );
423
428 virtual raw_t read( int ch );
429
434 virtual void read( raw_t *data );
435
440 virtual void read( microvolt_t *data );
441
442// constexpr static double pga_gain[] = { 0.2, 0.4, 0.8, 1, 2, 4, 8, 16 };
443 static double pga_gain[];
444
445 enum GainPGA : uint8_t {
446 G_PGA_x_0_2 = 0,
447 G_PGA_x_0_4,
448 G_PGA_x_0_8,
449 G_PGA_x_1_0,
450 G_PGA_x_2_0,
451 G_PGA_x_4_0,
452 G_PGA_x_8_0,
453 G_PGA_x16_0,
454 };
455
456 enum class Register16 : uint16_t {
457 CH_CONFIG0 = 0x20,
458 CH_CONFIG1 = 0x21,
459 CH_CONFIG2 = 0x22,
460 CH_CONFIG3 = 0x23,
461 CH_CONFIG4 = 0x24,
462 CRC_CONF_REGS = 0x25,
463 CRC_COEF_REGS = 0x26,
464 CRC_TRIM_REGS = 0x27,
465 GPI_DATA = 0x29,
466 GPIO_CONFIG0 = 0x2A,
467 GPIO_CONFIG1 = 0x2B,
468 GPIO_CONFIG2 = 0x2C,
469 GPI_EDGE_POS = 0x2D,
470 GPI_EDGE_NEG = 0x2E,
471 GPO_DATA = 0x2F,
472 SYS_CONFIG0 = 0x30,
473 SYS_STATUS0 = 0x31,
474 GLOBAL_ALARM_ENABLE = 0x32,
475 GLOBAL_ALARM_INTERRUPT = 0x33,
476 DIE_TEMP = 0x34,
477 CH_STATUS0 = 0x35,
478 CH_STATUS1 = 0x36,
479 THRS_TEMP = 0x37,
480 PN2 = 0x7C,
481 PN1 = 0x7D,
482 PN0 = 0x7E,
483 CRC_TRIM_INT = 0x7F,
484 };
485
486 enum class Register24 : uint16_t {
487 CH_DATA0 = 0x40,
488 CH_DATA1 = 0x41,
489 CH_DATA2 = 0x42,
490 CH_DATA3 = 0x43,
491 CH_DATA4 = 0x44,
492 CH_DATA5 = 0x45,
493 CH_DATA6 = 0x46,
494 CH_DATA7 = 0x47,
495 CH_DATA8 = 0x48,
496 CH_DATA9 = 0x4A,
497 CH_DATA10 = 0x4B,
498 CH_DATA11 = 0x4C,
499 CH_DATA13 = 0x4D,
500 CH_DATA14 = 0x4E,
501 CH_DATA15 = 0x4F,
502 CH_CONFIG5_0 = 0x50,
503 CH_CONFIG5_1 = 0x51,
504 CH_CONFIG5_2 = 0x52,
505 CH_CONFIG5_3 = 0x53,
506 CH_CONFIG5_4 = 0x54,
507 CH_CONFIG5_5 = 0x55,
508 CH_CONFIG5_6 = 0x56,
509 CH_CONFIG5_7 = 0x57,
510 CH_CONFIG5_8 = 0x58,
511 CH_CONFIG5_9 = 0x59,
512 CH_CONFIG5_10 = 0x5A,
513 CH_CONFIG5_11 = 0x5B,
514 CH_CONFIG5_12 = 0x5C,
515 CH_CONFIG5_13 = 0x5D,
516 CH_CONFIG5_14 = 0x5E,
517 CH_CONFIG5_15 = 0x5F,
518 CH_CONFIG6_0 = 0x60,
519 CH_CONFIG6_1 = 0x61,
520 CH_CONFIG6_2 = 0x62,
521 CH_CONFIG6_3 = 0x63,
522 CH_CONFIG6_4 = 0x64,
523 CH_CONFIG6_5 = 0x65,
524 CH_CONFIG6_6 = 0x66,
525 CH_CONFIG6_7 = 0x67,
526 CH_CONFIG6_8 = 0x68,
527 CH_CONFIG6_9 = 0x69,
528 CH_CONFIG6_10 = 0x6A,
529 CH_CONFIG6_11 = 0x6B,
530 CH_CONFIG6_12 = 0x6C,
531 CH_CONFIG6_13 = 0x6D,
532 CH_CONFIG6_14 = 0x6E,
533 CH_CONFIG6_15 = 0x6F,
534 GAIN_COEFF0 = 0x80,
535 GAIN_COEFF1 = 0x81,
536 GAIN_COEFF2 = 0x82,
537 GAIN_COEFF3 = 0x83,
538 GAIN_COEFF4 = 0x84,
539 GAIN_COEFF5 = 0x85,
540 GAIN_COEFF6 = 0x86,
541 GAIN_COEFF7 = 0x87,
542 GAIN_COEFF8 = 0x88,
543 GAIN_COEFF9 = 0x89,
544 GAIN_COEFF10 = 0x8A,
545 GAIN_COEFF11 = 0x8B,
546 GAIN_COEFF12 = 0x8C,
547 GAIN_COEFF13 = 0x8D,
548 GAIN_COEFF14 = 0x8E,
549 GAIN_COEFF15 = 0x8F,
550 OFFSET_COEFF0 = 0x90,
551 OFFSET_COEFF1 = 0x91,
552 OFFSET_COEFF2 = 0x92,
553 OFFSET_COEFF3 = 0x93,
554 OFFSET_COEFF4 = 0x94,
555 OFFSET_COEFF5 = 0x95,
556 OFFSET_COEFF6 = 0x96,
557 OFFSET_COEFF7 = 0x97,
558 OFFSET_COEFF8 = 0x98,
559 OFFSET_COEFF9 = 0x99,
560 OFFSET_COEFF10 = 0x9A,
561 OFFSET_COEFF11 = 0x9B,
562 OFFSET_COEFF12 = 0x9C,
563 OFFSET_COEFF13 = 0x9D,
564 OFFSET_COEFF14 = 0x9E,
565 OFFSET_COEFF15 = 0x9F,
566 OPT_COEF0 = 0xA0,
567 OPT_COEF1 = 0xA1,
568 OPT_COEF2 = 0xA2,
569 OPT_COEF3 = 0xA3,
570 OPT_COEF4 = 0xA4,
571 OPT_COEF5 = 0xA5,
572 OPT_COEF6 = 0xA6,
573 OPT_COEF7 = 0xA7,
574 OPT_COEF8 = 0xA8,
575 OPT_COEF9 = 0xA9,
576 OPT_COEF10 = 0xAA,
577 OPT_COEF11 = 0xAB,
578 OPT_COEF12 = 0xAC,
579 OPT_COEF13 = 0xAD,
580 SERIAL1 = 0xAE,
581 SERIAL0 = 0xAF,
582 };
583
584 enum Command : uint16_t {
585 CMD_CH0 = 0x0000,
586 CMD_CH1 = 0x0001,
587 CMD_CH2 = 0x0002,
588 CMD_CH3 = 0x0003,
589 CMD_CH4 = 0x0004,
590 CMD_CH5 = 0x0005,
591 CMD_CH6 = 0x0006,
592 CMD_CH7 = 0x0007,
593 CMD_CH8 = 0x0008,
594 CMD_CH9 = 0x0009,
595 CMD_CH10 = 0x000A,
596 CMD_CH11 = 0x000B,
597 CMD_CH12 = 0x000C,
598 CMD_CH13 = 0x000D,
599 CMD_CH14 = 0x000E,
600 CMD_CH15 = 0x000F,
601 CMD_ABORT = 0x0010,
602 CMD_END = 0x0011,
603 CMD_CLEAR_ALARM = 0x0012,
604 CMD_CLEAR_DATA = 0x0013,
605 CMD_RESET = 0x0014,
606 CMD_CLEAR_REG = 0x0015,
607 CMD_RELOAD = 0x0016,
608 TBD = 0x0017,
609 CMD_SS = 0x2000,
610 CMD_SC = 0x2001,
611 CMD_MM = 0x2002,
612 CMD_MC = 0x2003,
613 CMD_MS = 0x2004,
614 CMD_BURST_DATA = 0x2005,
615 CMD_CALC_CRC_CONFG = 0x2006,
616 CMD_CALC_CRC_COEF = 0x2007,
617 CMD_CALC_CRC_FAC = 0x2008,
618 };
619
624 virtual void command( uint16_t com );
625
631 virtual void reg( Register16 r, uint16_t value );
632
638 virtual void reg( Register24 r, uint32_t value );
639
646 virtual uint16_t reg( Register16 r );
647
654 virtual uint32_t reg( Register24 r );
655
663 template<typename T>
664 uint32_t bit_op( T rg, uint32_t mask, uint32_t value )
665 {
666 uint32_t v = reg( rg );
667
668 v &= mask;
669 v |= value & ~mask;
670
671 reg( rg, v );
672
673 return v;
674 }
675
680 uint32_t part_number( void );
681
686 uint8_t revision_number( void );
687
692 uint64_t serial_number( void );
693
698 float temperature( void );
699
705 void gain_offset_coeff( const ref_points &ref );
706
707 enum CalibrationError : int {
708 NoError = 0,
709 GainError = -1,
710 OffsetError = -2,
711 };
712
724 int self_calibrate( int pga_gain_index, int channel_selection = 15, int input_select = 0, double reference_source_voltage = 0, bool use_positive_side = true );
725
727 void blink_leds( void );
728};
729
730 class NAFE13388 : public NAFE13388_Base
731{
732public:
734 NAFE13388( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 2, int DRDY = 3, int SYN = 5, int nRESET = 6 );
735
737 virtual ~NAFE13388();
738};
739
740 class NAFE13388_UIM : public NAFE13388_Base
741{
742public:
744 NAFE13388_UIM( bool spi_addr = 0, bool highspeed_variant = false, int nINT = 3, int DRDY = 3, int SYN = 6, int nRESET = 7 );
745
747 virtual ~NAFE13388_UIM();
748
749 void blink_leds( void );
750};
751
752 inline NAFE13388_Base::Register16 operator+( NAFE13388_Base::Register16 rn, int n )
753{
754 return static_cast<NAFE13388_Base::Register16>( static_cast<uint16_t>( rn ) + n );
755}
756
757 inline NAFE13388_Base::Register16 operator+( int n, NAFE13388_Base::Register16 rn )
758{
759 return static_cast<NAFE13388_Base::Register16>( n + static_cast<uint16_t>( rn ) );
760}
761
762 inline NAFE13388_Base::Register24 operator+( NAFE13388_Base::Register24 rn, int n )
763{
764 return static_cast<NAFE13388_Base::Register24>( static_cast<uint16_t>( rn ) + n );
765}
766
767 inline NAFE13388_Base::Register24 operator+( int n, NAFE13388_Base::Register24 rn )
768{
769 return static_cast<NAFE13388_Base::Register24>( n + static_cast<uint16_t>( rn ) );
770}
771
772#endif // ARDUINO_AFE_DRIVER_H
operator+
NAFE13388_Base::Register16 operator+(NAFE13388_Base::Register16 rn, int n)
Definition AFE_NXP.h:752
SPI_for_AFE.h
AFE_base
Definition AFE_NXP.h:18
AFE_base::read
virtual void read(microvolt_t *data_ptr)=0
AFE_base::enable_logical_channel
virtual void enable_logical_channel(int ch)=0
AFE_base::start_continuous_conversion
virtual void start_continuous_conversion(void)=0
AFE_base::instance
static AFE_base * instance
Definition AFE_NXP.h:295
AFE_base::cbf_DRDY
static callback_fp_t cbf_DRDY
Definition AFE_NXP.h:287
AFE_base::close_logical_channel
virtual void close_logical_channel(void)=0
AFE_base::raw_t
int32_t raw_t
Definition AFE_NXP.h:22
AFE_base::AFE_base
AFE_base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input=2)
Definition AFE_NXP.cpp:70
AFE_base::microvolt_t
double microvolt_t
Definition AFE_NXP.h:23
AFE_base::use_DRDY_trigger
void use_DRDY_trigger(bool use=true)
Definition AFE_NXP.cpp:188
AFE_base::~AFE_base
virtual ~AFE_base()
Definition AFE_NXP.cpp:83
AFE_base::open_logical_channel
virtual void open_logical_channel(int ch, const uint16_t(&cc)[4])=0
AFE_base::DRDY_cb
static void DRDY_cb()
Definition AFE_NXP.cpp:111
AFE_base::pin_nINT
int pin_nINT
Definition AFE_NXP.h:256
AFE_base::set_DRDY_callback
virtual void set_DRDY_callback(callback_fp_t fnc)
Definition AFE_NXP.cpp:106
AFE_base::pin_DRDY_input
int pin_DRDY_input
Definition AFE_NXP.h:260
AFE_base::init
virtual void init(void)
Definition AFE_NXP.cpp:87
AFE_base::timeout_limit
static constexpr uint32_t timeout_limit
Definition AFE_NXP.h:281
AFE_base::begin
virtual void begin(void)
Definition AFE_NXP.cpp:97
AFE_base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)=0
AFE_base::drdy_delay
double drdy_delay(int ch)
Definition AFE_NXP.h:229
AFE_base::raw2mv
double raw2mv(int ch, raw_t value)
Definition AFE_NXP.h:201
AFE_base::LV_mux_sel
LV_mux_sel
Definition AFE_NXP.h:149
AFE_base::VADD_REF2
@ VADD_REF2
Definition AFE_NXP.h:153
AFE_base::HV_MUX
@ HV_MUX
Definition AFE_NXP.h:156
AFE_base::REF2_VHSS
@ REF2_VHSS
Definition AFE_NXP.h:155
AFE_base::GPIO0_GPIO1
@ GPIO0_GPIO1
Definition AFE_NXP.h:151
AFE_base::REF2_REF2
@ REF2_REF2
Definition AFE_NXP.h:150
AFE_base::REFCOARSE_REF2
@ REFCOARSE_REF2
Definition AFE_NXP.h:152
AFE_base::VHDD_REF2
@ VHDD_REF2
Definition AFE_NXP.h:154
AFE_base::highspeed_variant
bool highspeed_variant
Definition AFE_NXP.h:255
AFE_base::enabled_logical_channels
int enabled_logical_channels(void)
Definition AFE_NXP.h:242
AFE_base::reset
virtual void reset(bool hardware_reset=false)=0
AFE_base::drdy_count
uint32_t drdy_count
Definition AFE_NXP.h:285
AFE_base::bit_count
int bit_count(uint32_t value)
Definition AFE_NXP.cpp:152
AFE_base::coeff_uV
double coeff_uV[16]
Definition AFE_NXP.h:271
AFE_base::read
virtual void read(raw_t *data_ptr)=0
AFE_base::start
virtual void start(int ch)=0
AFE_base::default_drdy_cb
void default_drdy_cb()
Definition AFE_NXP.cpp:123
AFE_base::raw2uv
double raw2uv(int ch, raw_t value)
Definition AFE_NXP.h:164
AFE_base::callback_fp_t
void(* callback_fp_t)(void)
Definition AFE_NXP.h:46
AFE_base::start_and_read
virtual raw_t start_and_read(int ch)
Definition AFE_NXP.cpp:129
AFE_base::enabled_channels
int enabled_channels
Definition AFE_NXP.h:265
AFE_base::sequence_order
uint8_t sequence_order[16]
Definition AFE_NXP.h:268
AFE_base::static_default_drdy_cb
static void static_default_drdy_cb()
Definition AFE_NXP.cpp:117
AFE_base::start
virtual void start(void)=0
AFE_base::wait_conversion_complete
int wait_conversion_complete(double delay=-1.0)
Definition AFE_NXP.cpp:165
AFE_base::close_logical_channel
virtual void close_logical_channel(int ch)=0
AFE_base::drdy_flag
volatile bool drdy_flag
Definition AFE_NXP.h:286
AFE_base::pin_SYN
int pin_SYN
Definition AFE_NXP.h:258
AFE_base::delay_accuracy
static double delay_accuracy
Definition AFE_NXP.h:279
AFE_base::ch_delay
double ch_delay[16]
Definition AFE_NXP.h:277
AFE_base::mux_setting
int mux_setting[16]
Definition AFE_NXP.h:274
AFE_base::boot
virtual void boot(void)=0
AFE_base::pin_nRESET
int pin_nRESET
Definition AFE_NXP.h:259
AFE_base::coeff_mV
double coeff_mV(int ch)
Definition AFE_NXP.h:220
AFE_base::dev_add
bool dev_add
Definition AFE_NXP.h:254
AFE_base::start_and_read
void start_and_read(T data)
Definition AFE_NXP.h:138
AFE_base::drdy_delay
double drdy_delay(void)
Definition AFE_NXP.h:236
AFE_base::read
virtual raw_t read(int ch)=0
AFE_base::raw2v
double raw2v(int ch, raw_t value)
Definition AFE_NXP.h:211
AFE_base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)=0
AFE_base::pin_DRDY
int pin_DRDY
Definition AFE_NXP.h:257
AFE_base::total_delay
double total_delay
Definition AFE_NXP.h:278
LogicalChannel_Base::~LogicalChannel_Base
virtual ~LogicalChannel_Base()
Definition AFE_NXP.h:302
LogicalChannel_Base::operator+
double operator+(T v)
Definition AFE_NXP.h:312
LogicalChannel_Base::operator-
friend double operator-(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:317
LogicalChannel_Base::read
T read(void)
LogicalChannel_Base::LogicalChannel_Base
LogicalChannel_Base()
Definition AFE_NXP.h:301
LogicalChannel_Base::enable
void enable(void)
Definition AFE_NXP.cpp:14
LogicalChannel_Base::afe_ptr
AFE_base * afe_ptr
Definition AFE_NXP.h:322
LogicalChannel_Base::operator-
double operator-(T v)
Definition AFE_NXP.h:313
LogicalChannel_Base::operator*
double operator*(T v)
Definition AFE_NXP.h:314
LogicalChannel_Base::operator/
friend double operator/(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:319
LogicalChannel_Base::operator*
friend double operator*(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:318
LogicalChannel_Base::operator+
friend double operator+(T v, LogicalChannel_Base lc)
Definition AFE_NXP.h:316
LogicalChannel_Base::operator/
double operator/(T v)
Definition AFE_NXP.h:315
LogicalChannel_Base::ch_number
int ch_number
Definition AFE_NXP.h:321
LogicalChannel_Base::disable
void disable(void)
Definition AFE_NXP.cpp:19
NAFE13388_Base::LogicalChannel
Definition AFE_NXP.h:372
NAFE13388_Base::LogicalChannel::~LogicalChannel
virtual ~LogicalChannel()
Definition AFE_NXP.cpp:51
NAFE13388_Base::LogicalChannel::LogicalChannel
LogicalChannel()
Definition AFE_NXP.cpp:47
NAFE13388_Base::LogicalChannel::configure
void configure(const uint16_t(&cc)[4])
Definition AFE_NXP.cpp:56
NAFE13388_Base::start_continuous_conversion
virtual void start_continuous_conversion()
Definition AFE_NXP.cpp:390
NAFE13388_Base::NAFE13388_Base
NAFE13388_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET)
Definition AFE_NXP.cpp:202
NAFE13388_Base::boot
virtual void boot(void)
Definition AFE_NXP.cpp:216
NAFE13388_Base::gain_offset_coeff
void gain_offset_coeff(const ref_points &ref)
Definition AFE_NXP.cpp:469
NAFE13388_Base::calc_delay
double calc_delay(int ch)
Definition AFE_NXP.cpp:301
NAFE13388_Base::command
virtual void command(uint16_t com)
Definition AFE_NXP.cpp:420
NAFE13388_Base::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:605
NAFE13388_Base::read
virtual raw_t read(int ch)
Definition AFE_NXP.cpp:400
NAFE13388_Base::logical_channel
LogicalChannel logical_channel[16]
Definition AFE_NXP.h:381
NAFE13388_Base::pga_gain
static double pga_gain[]
Definition AFE_NXP.h:664
NAFE13388_Base::bit_op
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
Definition AFE_NXP.h:664
NAFE13388_Base::self_calibrate
int self_calibrate(int pga_gain_index, int channel_selection=15, int input_select=0, double reference_source_voltage=0, bool use_positive_side=true)
Definition AFE_NXP.cpp:501
NAFE13388_Base::ref_points
struct NAFE13388_Base::_ref_points ref_points
NAFE13388_Base::start
virtual void start(void)
Definition AFE_NXP.cpp:385
NAFE13388_Base::reg
virtual void reg(Register16 r, uint16_t value)
Definition AFE_NXP.cpp:425
NAFE13388_Base::GainPGA
GainPGA
Definition AFE_NXP.h:445
NAFE13388_Base::G_PGA_x_0_8
@ G_PGA_x_0_8
Definition AFE_NXP.h:448
NAFE13388_Base::G_PGA_x_0_4
@ G_PGA_x_0_4
Definition AFE_NXP.h:447
NAFE13388_Base::G_PGA_x_4_0
@ G_PGA_x_4_0
Definition AFE_NXP.h:451
NAFE13388_Base::G_PGA_x16_0
@ G_PGA_x16_0
Definition AFE_NXP.h:453
NAFE13388_Base::G_PGA_x_8_0
@ G_PGA_x_8_0
Definition AFE_NXP.h:452
NAFE13388_Base::G_PGA_x_0_2
@ G_PGA_x_0_2
Definition AFE_NXP.h:446
NAFE13388_Base::G_PGA_x_1_0
@ G_PGA_x_1_0
Definition AFE_NXP.h:449
NAFE13388_Base::G_PGA_x_2_0
@ G_PGA_x_2_0
Definition AFE_NXP.h:450
NAFE13388_Base::reference_point
struct NAFE13388_Base::_reference_point reference_point
NAFE13388_Base::revision_number
uint8_t revision_number(void)
Definition AFE_NXP.cpp:450
NAFE13388_Base::close_logical_channel
virtual void close_logical_channel(void)
Definition AFE_NXP.cpp:373
NAFE13388_Base::Register24
Register24
Definition AFE_NXP.h:486
NAFE13388_Base::Register24::OFFSET_COEFF10
@ OFFSET_COEFF10
Definition AFE_NXP.h:560
NAFE13388_Base::Register24::CH_DATA2
@ CH_DATA2
Definition AFE_NXP.h:489
NAFE13388_Base::Register24::CH_CONFIG5_7
@ CH_CONFIG5_7
Definition AFE_NXP.h:509
NAFE13388_Base::Register24::CH_DATA3
@ CH_DATA3
Definition AFE_NXP.h:490
NAFE13388_Base::Register24::OFFSET_COEFF3
@ OFFSET_COEFF3
Definition AFE_NXP.h:553
NAFE13388_Base::Register24::CH_CONFIG5_2
@ CH_CONFIG5_2
Definition AFE_NXP.h:504
NAFE13388_Base::Register24::CH_CONFIG6_14
@ CH_CONFIG6_14
Definition AFE_NXP.h:532
NAFE13388_Base::Register24::CH_CONFIG5_5
@ CH_CONFIG5_5
Definition AFE_NXP.h:507
NAFE13388_Base::Register24::GAIN_COEFF5
@ GAIN_COEFF5
Definition AFE_NXP.h:539
NAFE13388_Base::Register24::CH_CONFIG6_11
@ CH_CONFIG6_11
Definition AFE_NXP.h:529
NAFE13388_Base::Register24::CH_DATA9
@ CH_DATA9
Definition AFE_NXP.h:496
NAFE13388_Base::Register24::OFFSET_COEFF0
@ OFFSET_COEFF0
Definition AFE_NXP.h:550
NAFE13388_Base::Register24::CH_CONFIG5_4
@ CH_CONFIG5_4
Definition AFE_NXP.h:506
NAFE13388_Base::Register24::CH_DATA15
@ CH_DATA15
Definition AFE_NXP.h:501
NAFE13388_Base::Register24::OPT_COEF4
@ OPT_COEF4
Definition AFE_NXP.h:570
NAFE13388_Base::Register24::GAIN_COEFF4
@ GAIN_COEFF4
Definition AFE_NXP.h:538
NAFE13388_Base::Register24::CH_CONFIG6_10
@ CH_CONFIG6_10
Definition AFE_NXP.h:528
NAFE13388_Base::Register24::OFFSET_COEFF15
@ OFFSET_COEFF15
Definition AFE_NXP.h:565
NAFE13388_Base::Register24::OFFSET_COEFF8
@ OFFSET_COEFF8
Definition AFE_NXP.h:558
NAFE13388_Base::Register24::OPT_COEF6
@ OPT_COEF6
Definition AFE_NXP.h:572
NAFE13388_Base::Register24::OFFSET_COEFF11
@ OFFSET_COEFF11
Definition AFE_NXP.h:561
NAFE13388_Base::Register24::CH_CONFIG5_10
@ CH_CONFIG5_10
Definition AFE_NXP.h:512
NAFE13388_Base::Register24::CH_CONFIG6_5
@ CH_CONFIG6_5
Definition AFE_NXP.h:523
NAFE13388_Base::Register24::CH_DATA5
@ CH_DATA5
Definition AFE_NXP.h:492
NAFE13388_Base::Register24::CH_CONFIG5_1
@ CH_CONFIG5_1
Definition AFE_NXP.h:503
NAFE13388_Base::Register24::GAIN_COEFF12
@ GAIN_COEFF12
Definition AFE_NXP.h:546
NAFE13388_Base::Register24::GAIN_COEFF0
@ GAIN_COEFF0
Definition AFE_NXP.h:534
NAFE13388_Base::Register24::CH_CONFIG6_3
@ CH_CONFIG6_3
Definition AFE_NXP.h:521
NAFE13388_Base::Register24::GAIN_COEFF15
@ GAIN_COEFF15
Definition AFE_NXP.h:549
NAFE13388_Base::Register24::CH_CONFIG6_8
@ CH_CONFIG6_8
Definition AFE_NXP.h:526
NAFE13388_Base::Register24::CH_CONFIG5_15
@ CH_CONFIG5_15
Definition AFE_NXP.h:517
NAFE13388_Base::Register24::CH_DATA13
@ CH_DATA13
Definition AFE_NXP.h:499
NAFE13388_Base::Register24::GAIN_COEFF14
@ GAIN_COEFF14
Definition AFE_NXP.h:548
NAFE13388_Base::Register24::CH_DATA4
@ CH_DATA4
Definition AFE_NXP.h:491
NAFE13388_Base::Register24::OPT_COEF12
@ OPT_COEF12
Definition AFE_NXP.h:578
NAFE13388_Base::Register24::OFFSET_COEFF5
@ OFFSET_COEFF5
Definition AFE_NXP.h:555
NAFE13388_Base::Register24::OFFSET_COEFF4
@ OFFSET_COEFF4
Definition AFE_NXP.h:554
NAFE13388_Base::Register24::CH_CONFIG6_13
@ CH_CONFIG6_13
Definition AFE_NXP.h:531
NAFE13388_Base::Register24::OPT_COEF5
@ OPT_COEF5
Definition AFE_NXP.h:571
NAFE13388_Base::Register24::OPT_COEF2
@ OPT_COEF2
Definition AFE_NXP.h:568
NAFE13388_Base::Register24::CH_CONFIG5_6
@ CH_CONFIG5_6
Definition AFE_NXP.h:508
NAFE13388_Base::Register24::CH_CONFIG6_7
@ CH_CONFIG6_7
Definition AFE_NXP.h:525
NAFE13388_Base::Register24::GAIN_COEFF11
@ GAIN_COEFF11
Definition AFE_NXP.h:545
NAFE13388_Base::Register24::CH_DATA8
@ CH_DATA8
Definition AFE_NXP.h:495
NAFE13388_Base::Register24::CH_CONFIG5_9
@ CH_CONFIG5_9
Definition AFE_NXP.h:511
NAFE13388_Base::Register24::GAIN_COEFF1
@ GAIN_COEFF1
Definition AFE_NXP.h:535
NAFE13388_Base::Register24::OFFSET_COEFF7
@ OFFSET_COEFF7
Definition AFE_NXP.h:557
NAFE13388_Base::Register24::CH_DATA6
@ CH_DATA6
Definition AFE_NXP.h:493
NAFE13388_Base::Register24::GAIN_COEFF2
@ GAIN_COEFF2
Definition AFE_NXP.h:536
NAFE13388_Base::Register24::GAIN_COEFF10
@ GAIN_COEFF10
Definition AFE_NXP.h:544
NAFE13388_Base::Register24::GAIN_COEFF3
@ GAIN_COEFF3
Definition AFE_NXP.h:537
NAFE13388_Base::Register24::GAIN_COEFF8
@ GAIN_COEFF8
Definition AFE_NXP.h:542
NAFE13388_Base::Register24::OPT_COEF7
@ OPT_COEF7
Definition AFE_NXP.h:573
NAFE13388_Base::Register24::CH_DATA10
@ CH_DATA10
Definition AFE_NXP.h:497
NAFE13388_Base::Register24::CH_DATA7
@ CH_DATA7
Definition AFE_NXP.h:494
NAFE13388_Base::Register24::OFFSET_COEFF9
@ OFFSET_COEFF9
Definition AFE_NXP.h:559
NAFE13388_Base::Register24::CH_CONFIG6_2
@ CH_CONFIG6_2
Definition AFE_NXP.h:520
NAFE13388_Base::Register24::OPT_COEF9
@ OPT_COEF9
Definition AFE_NXP.h:575
NAFE13388_Base::Register24::CH_DATA11
@ CH_DATA11
Definition AFE_NXP.h:498
NAFE13388_Base::Register24::CH_CONFIG5_11
@ CH_CONFIG5_11
Definition AFE_NXP.h:513
NAFE13388_Base::Register24::GAIN_COEFF6
@ GAIN_COEFF6
Definition AFE_NXP.h:540
NAFE13388_Base::Register24::CH_CONFIG6_12
@ CH_CONFIG6_12
Definition AFE_NXP.h:530
NAFE13388_Base::Register24::OFFSET_COEFF6
@ OFFSET_COEFF6
Definition AFE_NXP.h:556
NAFE13388_Base::Register24::GAIN_COEFF9
@ GAIN_COEFF9
Definition AFE_NXP.h:543
NAFE13388_Base::Register24::CH_CONFIG5_3
@ CH_CONFIG5_3
Definition AFE_NXP.h:505
NAFE13388_Base::Register24::CH_CONFIG5_8
@ CH_CONFIG5_8
Definition AFE_NXP.h:510
NAFE13388_Base::Register24::CH_DATA14
@ CH_DATA14
Definition AFE_NXP.h:500
NAFE13388_Base::Register24::SERIAL0
@ SERIAL0
Definition AFE_NXP.h:581
NAFE13388_Base::Register24::CH_DATA1
@ CH_DATA1
Definition AFE_NXP.h:488
NAFE13388_Base::Register24::OPT_COEF13
@ OPT_COEF13
Definition AFE_NXP.h:579
NAFE13388_Base::Register24::CH_CONFIG6_9
@ CH_CONFIG6_9
Definition AFE_NXP.h:527
NAFE13388_Base::Register24::OFFSET_COEFF1
@ OFFSET_COEFF1
Definition AFE_NXP.h:551
NAFE13388_Base::Register24::CH_CONFIG6_4
@ CH_CONFIG6_4
Definition AFE_NXP.h:522
NAFE13388_Base::Register24::OFFSET_COEFF13
@ OFFSET_COEFF13
Definition AFE_NXP.h:563
NAFE13388_Base::Register24::OPT_COEF0
@ OPT_COEF0
Definition AFE_NXP.h:566
NAFE13388_Base::Register24::CH_CONFIG5_0
@ CH_CONFIG5_0
Definition AFE_NXP.h:502
NAFE13388_Base::Register24::OPT_COEF11
@ OPT_COEF11
Definition AFE_NXP.h:577
NAFE13388_Base::Register24::GAIN_COEFF7
@ GAIN_COEFF7
Definition AFE_NXP.h:541
NAFE13388_Base::Register24::CH_CONFIG6_15
@ CH_CONFIG6_15
Definition AFE_NXP.h:533
NAFE13388_Base::Register24::OFFSET_COEFF12
@ OFFSET_COEFF12
Definition AFE_NXP.h:562
NAFE13388_Base::Register24::OFFSET_COEFF14
@ OFFSET_COEFF14
Definition AFE_NXP.h:564
NAFE13388_Base::Register24::CH_CONFIG6_0
@ CH_CONFIG6_0
Definition AFE_NXP.h:518
NAFE13388_Base::Register24::OPT_COEF1
@ OPT_COEF1
Definition AFE_NXP.h:567
NAFE13388_Base::Register24::OPT_COEF10
@ OPT_COEF10
Definition AFE_NXP.h:576
NAFE13388_Base::Register24::CH_CONFIG5_14
@ CH_CONFIG5_14
Definition AFE_NXP.h:516
NAFE13388_Base::Register24::OPT_COEF3
@ OPT_COEF3
Definition AFE_NXP.h:569
NAFE13388_Base::Register24::SERIAL1
@ SERIAL1
Definition AFE_NXP.h:580
NAFE13388_Base::Register24::CH_DATA0
@ CH_DATA0
Definition AFE_NXP.h:487
NAFE13388_Base::Register24::CH_CONFIG6_1
@ CH_CONFIG6_1
Definition AFE_NXP.h:519
NAFE13388_Base::Register24::CH_CONFIG5_12
@ CH_CONFIG5_12
Definition AFE_NXP.h:514
NAFE13388_Base::Register24::OFFSET_COEFF2
@ OFFSET_COEFF2
Definition AFE_NXP.h:552
NAFE13388_Base::Register24::GAIN_COEFF13
@ GAIN_COEFF13
Definition AFE_NXP.h:547
NAFE13388_Base::Register24::OPT_COEF8
@ OPT_COEF8
Definition AFE_NXP.h:574
NAFE13388_Base::Register24::CH_CONFIG5_13
@ CH_CONFIG5_13
Definition AFE_NXP.h:515
NAFE13388_Base::Register24::CH_CONFIG6_6
@ CH_CONFIG6_6
Definition AFE_NXP.h:524
NAFE13388_Base::Command
Command
Definition AFE_NXP.h:584
NAFE13388_Base::CMD_MM
@ CMD_MM
Definition AFE_NXP.h:611
NAFE13388_Base::CMD_CLEAR_DATA
@ CMD_CLEAR_DATA
Definition AFE_NXP.h:604
NAFE13388_Base::CMD_BURST_DATA
@ CMD_BURST_DATA
Definition AFE_NXP.h:614
NAFE13388_Base::CMD_RELOAD
@ CMD_RELOAD
Definition AFE_NXP.h:607
NAFE13388_Base::CMD_CH3
@ CMD_CH3
Definition AFE_NXP.h:588
NAFE13388_Base::CMD_MC
@ CMD_MC
Definition AFE_NXP.h:612
NAFE13388_Base::CMD_CH11
@ CMD_CH11
Definition AFE_NXP.h:596
NAFE13388_Base::CMD_CALC_CRC_COEF
@ CMD_CALC_CRC_COEF
Definition AFE_NXP.h:616
NAFE13388_Base::CMD_CH2
@ CMD_CH2
Definition AFE_NXP.h:587
NAFE13388_Base::CMD_MS
@ CMD_MS
Definition AFE_NXP.h:613
NAFE13388_Base::CMD_SS
@ CMD_SS
Definition AFE_NXP.h:609
NAFE13388_Base::CMD_CH8
@ CMD_CH8
Definition AFE_NXP.h:593
NAFE13388_Base::CMD_CALC_CRC_CONFG
@ CMD_CALC_CRC_CONFG
Definition AFE_NXP.h:615
NAFE13388_Base::CMD_CALC_CRC_FAC
@ CMD_CALC_CRC_FAC
Definition AFE_NXP.h:617
NAFE13388_Base::CMD_CLEAR_ALARM
@ CMD_CLEAR_ALARM
Definition AFE_NXP.h:603
NAFE13388_Base::CMD_RESET
@ CMD_RESET
Definition AFE_NXP.h:605
NAFE13388_Base::CMD_SC
@ CMD_SC
Definition AFE_NXP.h:610
NAFE13388_Base::CMD_CH5
@ CMD_CH5
Definition AFE_NXP.h:590
NAFE13388_Base::CMD_CH9
@ CMD_CH9
Definition AFE_NXP.h:594
NAFE13388_Base::CMD_CH14
@ CMD_CH14
Definition AFE_NXP.h:599
NAFE13388_Base::CMD_CH10
@ CMD_CH10
Definition AFE_NXP.h:595
NAFE13388_Base::CMD_CLEAR_REG
@ CMD_CLEAR_REG
Definition AFE_NXP.h:606
NAFE13388_Base::CMD_CH0
@ CMD_CH0
Definition AFE_NXP.h:585
NAFE13388_Base::CMD_CH13
@ CMD_CH13
Definition AFE_NXP.h:598
NAFE13388_Base::TBD
@ TBD
Definition AFE_NXP.h:608
NAFE13388_Base::CMD_CH1
@ CMD_CH1
Definition AFE_NXP.h:586
NAFE13388_Base::CMD_CH15
@ CMD_CH15
Definition AFE_NXP.h:600
NAFE13388_Base::CMD_CH7
@ CMD_CH7
Definition AFE_NXP.h:592
NAFE13388_Base::CMD_CH6
@ CMD_CH6
Definition AFE_NXP.h:591
NAFE13388_Base::CMD_ABORT
@ CMD_ABORT
Definition AFE_NXP.h:601
NAFE13388_Base::CMD_CH4
@ CMD_CH4
Definition AFE_NXP.h:589
NAFE13388_Base::CMD_CH12
@ CMD_CH12
Definition AFE_NXP.h:597
NAFE13388_Base::CMD_END
@ CMD_END
Definition AFE_NXP.h:602
NAFE13388_Base::DRDY_by_sequencer_done
virtual void DRDY_by_sequencer_done(bool flag=true)
Definition AFE_NXP.cpp:395
NAFE13388_Base::serial_number
uint64_t serial_number(void)
Definition AFE_NXP.cpp:455
NAFE13388_Base::channel_info_update
void channel_info_update(uint16_t value)
Definition AFE_NXP.cpp:276
NAFE13388_Base::~NAFE13388_Base
virtual ~NAFE13388_Base()
Definition AFE_NXP.cpp:212
NAFE13388_Base::enable_logical_channel
void enable_logical_channel(int ch)
Definition AFE_NXP.cpp:357
NAFE13388_Base::reset
virtual void reset(bool hardware_reset=false)
Definition AFE_NXP.cpp:224
NAFE13388_Base::part_number
uint32_t part_number(void)
Definition AFE_NXP.cpp:445
NAFE13388_Base::open_logical_channel
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
Definition AFE_NXP.cpp:351
NAFE13388_Base::ch_setting_t
uint16_t[4] ch_setting_t
Definition AFE_NXP.h:328
NAFE13388_Base::Register16
Register16
Definition AFE_NXP.h:456
NAFE13388_Base::Register16::CH_CONFIG1
@ CH_CONFIG1
Definition AFE_NXP.h:458
NAFE13388_Base::Register16::CRC_TRIM_INT
@ CRC_TRIM_INT
Definition AFE_NXP.h:483
NAFE13388_Base::Register16::GLOBAL_ALARM_INTERRUPT
@ GLOBAL_ALARM_INTERRUPT
Definition AFE_NXP.h:475
NAFE13388_Base::Register16::CH_CONFIG3
@ CH_CONFIG3
Definition AFE_NXP.h:460
NAFE13388_Base::Register16::CH_CONFIG2
@ CH_CONFIG2
Definition AFE_NXP.h:459
NAFE13388_Base::Register16::CRC_TRIM_REGS
@ CRC_TRIM_REGS
Definition AFE_NXP.h:464
NAFE13388_Base::Register16::GPIO_CONFIG0
@ GPIO_CONFIG0
Definition AFE_NXP.h:466
NAFE13388_Base::Register16::PN1
@ PN1
Definition AFE_NXP.h:481
NAFE13388_Base::Register16::CRC_COEF_REGS
@ CRC_COEF_REGS
Definition AFE_NXP.h:463
NAFE13388_Base::Register16::GPI_EDGE_POS
@ GPI_EDGE_POS
Definition AFE_NXP.h:469
NAFE13388_Base::Register16::CH_STATUS0
@ CH_STATUS0
Definition AFE_NXP.h:477
NAFE13388_Base::Register16::CH_CONFIG4
@ CH_CONFIG4
Definition AFE_NXP.h:461
NAFE13388_Base::Register16::SYS_STATUS0
@ SYS_STATUS0
Definition AFE_NXP.h:473
NAFE13388_Base::Register16::THRS_TEMP
@ THRS_TEMP
Definition AFE_NXP.h:479
NAFE13388_Base::Register16::PN0
@ PN0
Definition AFE_NXP.h:482
NAFE13388_Base::Register16::GPIO_CONFIG2
@ GPIO_CONFIG2
Definition AFE_NXP.h:468
NAFE13388_Base::Register16::GPI_DATA
@ GPI_DATA
Definition AFE_NXP.h:465
NAFE13388_Base::Register16::GLOBAL_ALARM_ENABLE
@ GLOBAL_ALARM_ENABLE
Definition AFE_NXP.h:474
NAFE13388_Base::Register16::DIE_TEMP
@ DIE_TEMP
Definition AFE_NXP.h:476
NAFE13388_Base::Register16::CH_CONFIG0
@ CH_CONFIG0
Definition AFE_NXP.h:457
NAFE13388_Base::Register16::GPIO_CONFIG1
@ GPIO_CONFIG1
Definition AFE_NXP.h:467
NAFE13388_Base::Register16::CRC_CONF_REGS
@ CRC_CONF_REGS
Definition AFE_NXP.h:462
NAFE13388_Base::Register16::GPO_DATA
@ GPO_DATA
Definition AFE_NXP.h:471
NAFE13388_Base::Register16::GPI_EDGE_NEG
@ GPI_EDGE_NEG
Definition AFE_NXP.h:470
NAFE13388_Base::Register16::PN2
@ PN2
Definition AFE_NXP.h:480
NAFE13388_Base::Register16::CH_STATUS1
@ CH_STATUS1
Definition AFE_NXP.h:478
NAFE13388_Base::Register16::SYS_CONFIG0
@ SYS_CONFIG0
Definition AFE_NXP.h:472
NAFE13388_Base::temperature
float temperature(void)
Definition AFE_NXP.cpp:464
NAFE13388_Base::CalibrationError
CalibrationError
Definition AFE_NXP.h:707
NAFE13388_Base::NoError
@ NoError
Definition AFE_NXP.h:708
NAFE13388_Base::OffsetError
@ OffsetError
Definition AFE_NXP.h:710
NAFE13388_Base::GainError
@ GainError
Definition AFE_NXP.h:709
NAFE13388_UIM::NAFE13388_UIM
NAFE13388_UIM(bool spi_addr=0, bool highspeed_variant=false, int nINT=3, int DRDY=3, int SYN=6, int nRESET=7)
Definition AFE_NXP.cpp:623
NAFE13388_UIM::blink_leds
void blink_leds(void)
Definition AFE_NXP.cpp:632
NAFE13388_UIM::~NAFE13388_UIM
virtual ~NAFE13388_UIM()
Definition AFE_NXP.cpp:628
NAFE13388::~NAFE13388
virtual ~NAFE13388()
Definition AFE_NXP.cpp:617
NAFE13388::NAFE13388
NAFE13388(bool spi_addr=0, bool highspeed_variant=false, int nINT=2, int DRDY=3, int SYN=5, int nRESET=6)
Definition AFE_NXP.cpp:612
SPI_for_AFE
Definition SPI_for_AFE.h:23
NAFE13388_Base::_ref_points
Definition AFE_NXP.h:335
NAFE13388_Base::_ref_points::coeff_index
int coeff_index
Definition AFE_NXP.h:336
NAFE13388_Base::_ref_points::high
reference_point high
Definition AFE_NXP.h:337
NAFE13388_Base::_ref_points::low
reference_point low
Definition AFE_NXP.h:338
NAFE13388_Base::_ref_points::cal_index
int cal_index
Definition AFE_NXP.h:339
NAFE13388_Base::_reference_point
Definition AFE_NXP.h:330
NAFE13388_Base::_reference_point::voltage
double voltage
Definition AFE_NXP.h:331
NAFE13388_Base::_reference_point::data
int32_t data
Definition AFE_NXP.h:332