9#ifndef ARDUINO_AFE_DRIVER_H
10#define ARDUINO_AFE_DRIVER_H
37 virtual void begin(
void );
40 virtual void boot(
void ) = 0;
43 virtual void reset(
bool hardware_reset =
false ) = 0;
79 virtual void start(
int ch ) = 0;
113#ifdef NON_TEMPLATE_VERSION_FOR_START_AND_READ
152 return value *
coeff_uV[ ch ] * 1e-3;
162 return value *
coeff_uV[ ch ] * 1e-6;
229 virtual void init(
void );
260 virtual void boot(
void );
263 virtual void reset(
bool hardware_reset =
false );
273 virtual void open_logical_channel(
int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3 );
301 virtual void start(
int ch );
305 virtual void start(
void );
500 virtual void command( uint16_t com );
540 uint32_t
bit_op( T rg, uint32_t mask, uint32_t value )
542 uint32_t v =
reg( rg );
600 int self_calibrate(
int pga_gain_index,
int channel_selection = 15,
int input_select = 0,
double reference_source_voltage = 0,
bool use_positive_side =
true );
NAFE13388_Base::Register16 operator+(NAFE13388_Base::Register16 rn, int n)
virtual void start_continuous_conversion(void)=0
virtual void close_logical_channel(void)=0
void use_DRDY_trigger(bool use=true)
virtual void open_logical_channel(int ch, const uint16_t(&cc)[4])=0
AFE_base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET)
static constexpr uint32_t timeout_limit
static void DRDY_cb(void)
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)=0
double drdy_delay(int ch)
void default_drdy_cb(void)
double raw2mv(int ch, raw_t value)
int enabled_logical_channels(void)
virtual void reset(bool hardware_reset=false)=0
int bit_count(uint32_t value)
virtual void read(raw_t *data_ptr)=0
virtual void start(int ch)=0
double raw2uv(int ch, raw_t value)
virtual raw_t start_and_read(int ch)
virtual void start(void)=0
int wait_conversion_complete(double delay=-1.0)
virtual void close_logical_channel(int ch)=0
static double delay_accuracy
virtual void boot(void)=0
void start_and_read(T data)
virtual raw_t read(int ch)=0
double raw2v(int ch, raw_t value)
virtual void DRDY_by_sequencer_done(bool flag=true)=0
virtual void start_continuous_conversion()
NAFE13388_Base(bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET)
void gain_offset_coeff(const ref_points &ref)
double calc_delay(int ch)
virtual void command(uint16_t com)
virtual raw_t read(int ch)
uint32_t bit_op(T rg, uint32_t mask, uint32_t value)
int self_calibrate(int pga_gain_index, int channel_selection=15, int input_select=0, double reference_source_voltage=0, bool use_positive_side=true)
struct NAFE13388_Base::_ref_points ref_points
virtual void reg(Register16 r, uint16_t value)
struct NAFE13388_Base::_reference_point reference_point
uint8_t revision_number(void)
virtual void close_logical_channel(void)
virtual void DRDY_by_sequencer_done(bool flag=true)
uint64_t serial_number(void)
void channel_info_update(uint16_t value)
virtual ~NAFE13388_Base()
virtual void reset(bool hardware_reset=false)
uint32_t part_number(void)
virtual void open_logical_channel(int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t cc3)
NAFE13388_UIM(bool spi_addr=0, bool highspeed_variant=false, int nINT=3, int DRDY=4, int SYN=6, int nRESET=7)
NAFE13388(bool spi_addr=0, bool highspeed_variant=false, int nINT=2, int DRDY=3, int SYN=5, int nRESET=6)