PU2CLR QN8066 Arduino Library 1.3.0
Arduino Library for QN8066Devices - By Ricardo Lima Caratti
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#include <Arduino.h>
#include <Wire.h>
Go to the source code of this file.
Classes | |
union | qn8066_system1 |
System1 - Sets device modes (Address: 00h) More... | |
union | qn8066_system2 |
System2 - Sets device modes (Address: 01h) More... | |
union | qn8066_cca |
CCA - Sets CCA parameters ( Address: 02h) More... | |
union | qn8066_snr |
SRN - Estimate RF input CNR value( Address: 03h - Read Only) More... | |
union | qn8066_rssisig |
RSSISIG - In-band signal RSSI (Received signal strength indicator) dBuV value. dBuV=RSSI-49( Address: 04h - Read Only) More... | |
union | qn8066_cid1 |
CID1 - Device ID numbers ( Address: 05h - Read Only) More... | |
union | qn8066_cid2 |
CID2 - Device ID numbers ( Address: 06h - Read Only) More... | |
union | qn8066_xtal_div0 |
XTAL_DIV0 - Frequency select of reference clock source (Lower bits - Address: 07h - Write Only) More... | |
union | qn8066_xtal_div1 |
XTAL_DIV1 - Frequency select of reference clock source (Lower bits - Address: 08h - Write Only) More... | |
union | qn8066_xtal_div2 |
XTAL_DIV2 - Frequency select of reference clock source (Lower bits - Address: 09h - Write Only) More... | |
union | qn8066_status1 |
STATUS1 - System status ( Address: 0Ah - Read Only) More... | |
union | qn8066_rx_ch |
RX_CH - Lower 8 bit of 10-bit receiver channel index (Address: 0Bh - Write Only) More... | |
union | qn8066_ch_start |
CH_START - Lower 8 bits of 10-bit CCA(channel scan) start channel index (Address: 0Ch - Write Only) More... | |
union | qn8066_ch_stop |
CH_STOP - Lower 8 bits of 10-bit channel scan stop channel index (Address: 0Dh - Write Only) More... | |
union | qn8066_ch_step |
CH_STEP - Channel scan frequency step (Address: 0Eh - Write Only) More... | |
union | qn8066_rx_rds |
RDS - RDS data byte 0 to byte 7 (Address: 0Fh to 16h - Read Only) More... | |
union | qn8066_status2 |
STATUS2 - Receiver RDS status indicators (Address: 17h - Read Only) More... | |
union | qn8066_vol_ctl |
VOL_CT - Audio volume control (Address: 18h - Write Only) More... | |
union | qn8066_int_ctrl |
INT_CTRL - Receiver RDS control (Address: 19h - Write Only) More... | |
union | qn8066_status3 |
STATUS3 - Receiver audio peak level and AGC status (Address: 1Ah - Read Only) More... | |
union | qn8066_txch |
TXCH - Lower 8 bit of 10-bit transmitter channel index (Address: 1Bh - Read and Write) More... | |
union | qn8066_tx_rds |
RDS - RDS tx data from byte 0 to byte 7 (Address: 1Ch to 23h - Write Only) More... | |
union | qn8066_pac |
PAC - PA output power target control (Address: 24h - Write Only) More... | |
union | qn8066_fdev |
FDEV - Specify total TX frequency deviation (Address: 25h - Write Only) More... | |
union | qn8066_rds |
RDS - Specify transmit RDS frequency deviation (Address: 26h - Write Only) More... | |
union | qn8066_gplt |
GPLT - Transmitter soft chip threshold, gain of TX pilot (Address: 27h. More... | |
union | qn8066_reg_vga |
REG_VGA - X AGC gain (Address: 28h - Read and Write) More... | |
union | RDS_BLOCK1 |
RDS - First block (RDS_BLOCK1 datatype) More... | |
union | RDS_BLOCK2 |
Block 2 (RDS_BLOCK2 data type) More... | |
union | RDS_BLOCK3 |
Block 3 (RDS_BLOCK3 data type) More... | |
union | RDS_BLOCK4 |
Block 4 (RDS_BLOCK4 data type) More... | |
union | RDS_DATE_TIME |
union | WORD16 |
class | QN8066 |
QN8066 Class. More... | |
struct | qn8066_system1.arg |
struct | qn8066_system2.arg |
struct | qn8066_cca.arg |
struct | qn8066_cid1.arg |
struct | qn8066_cid2.arg |
struct | qn8066_xtal_div1.arg |
struct | qn8066_status1.arg |
struct | qn8066_ch_step.arg |
struct | qn8066_rx_rds.arg |
struct | qn8066_status2.arg |
struct | qn8066_vol_ctl.arg |
struct | qn8066_int_ctrl.arg |
struct | qn8066_status3.arg |
struct | qn8066_tx_rds.arg |
struct | qn8066_pac.arg |
struct | qn8066_rds.arg |
struct | qn8066_gplt.arg |
struct | qn8066_reg_vga.arg |
struct | RDS_BLOCK1.field |
struct | RDS_BLOCK2.commonFields |
struct | RDS_BLOCK2.group0Field |
struct | RDS_BLOCK2.group2Field |
struct | RDS_BLOCK4.utc |
struct | RDS_DATE_TIME.arg |
Macros | |
#define | QN8066_I2C_ADDRESS 0x21 |
QN8066 ARDUINO LIBRARY. | |
#define | QN8066_RESET_DELAY 1000 |
#define | QN8066_DELAY_COMMAND 2500 |
#define | QN_SYSTEM1 0x00 |
QN8066 Register addresses. | |
#define | QN_SYSTEM2 0x01 |
#define | QN_CCA 0x02 |
#define | QN_SNR 0x03 |
#define | QN_RSSISIG 0x04 |
#define | QN_CID1 0x05 |
#define | QN_CID2 0x06 |
#define | QN_XTAL_DIV0 0x07 |
#define | QN_XTAL_DIV1 0x08 |
#define | QN_XTAL_DIV2 0x09 |
#define | QN_STATUS1 0x0A |
#define | QN_RX_CH 0x0B |
#define | QN_CH_START 0x0C |
#define | QN_CH_STOP 0x0D |
#define | QN_CH_STEP 0x0E |
#define | QN_RX_RDSD0 0x0F |
#define | QN_RX_RDSD1 0x10 |
#define | QN_RX_RDSD2 0x11 |
#define | QN_RX_RDSD3 0x12 |
#define | QN_RX_RDSD4 0x13 |
#define | QN_RX_RDSD5 0x14 |
#define | QN_RX_RDSD6 0x15 |
#define | QN_RX_RDSD7 0x16 |
#define | QN_STATUS2 0x17 |
#define | QN_VOL_CTL 0x18 |
#define | QN_INT_CTRL 0x19 |
#define | QN_STATUS3 0x1A |
#define | QN_TXCH 0x1B |
#define | QN_TX_RDSD0 0x1C |
#define | QN_TX_RDSD1 0x1D |
#define | QN_TX_RDSD2 0x1E |
#define | QN_TX_RDSD3 0x1F |
#define | QN_TX_RDSD4 0x20 |
#define | QN_TX_RDSD5 0x21 |
#define | QN_TX_RDSD6 0x22 |
#define | QN_TX_RDSD7 0x23 |
#define | QN_PAC 0x24 |
#define | QN_FDEV 0x25 |
#define | QN_RDS 0x26 |
#define | QN_GPLT 0x27 |
#define | QN_REG_VGA 0x28 |
#define | QN_REGISTER_6E 0x6E |
#define | QN_REGISTER_49 0x49 |
union RDS_DATE_TIME |
Class Members | ||
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struct RDS_DATE_TIME.arg | arg | |
uint8_t | raw[6] |
struct RDS_DATE_TIME.arg |
#define QN8066_I2C_ADDRESS 0x21 |
QN8066 ARDUINO LIBRARY.
This is an Arduino library for the QN8066 FM RX/TX device (Digital FM Transceiver for Portable Devices).
The communication used by this library is I2C.
This file contains: const (#define), Defined Data type and Methods declarations
You can see a complete documentation on https://github.com/pu2clr/QN8066
There are examples that can help you in your project on https://github.com/pu2clr/QN8066/tree/master/examples
#define QN8066_RESET_DELAY 1000 |
#define QN8066_DELAY_COMMAND 2500 |
#define QN_SYSTEM1 0x00 |
QN8066 Register addresses.
#define QN_SYSTEM2 0x01 |
#define QN_CCA 0x02 |
#define QN_SNR 0x03 |
#define QN_RSSISIG 0x04 |
#define QN_CID1 0x05 |
#define QN_CID2 0x06 |
#define QN_XTAL_DIV0 0x07 |
#define QN_XTAL_DIV1 0x08 |
#define QN_XTAL_DIV2 0x09 |
#define QN_STATUS1 0x0A |
#define QN_RX_CH 0x0B |
#define QN_CH_START 0x0C |
#define QN_CH_STOP 0x0D |
#define QN_CH_STEP 0x0E |
#define QN_RX_RDSD0 0x0F |
#define QN_RX_RDSD1 0x10 |
#define QN_RX_RDSD2 0x11 |
#define QN_RX_RDSD3 0x12 |
#define QN_RX_RDSD4 0x13 |
#define QN_RX_RDSD5 0x14 |
#define QN_RX_RDSD6 0x15 |
#define QN_RX_RDSD7 0x16 |
#define QN_STATUS2 0x17 |
#define QN_VOL_CTL 0x18 |
#define QN_INT_CTRL 0x19 |
#define QN_STATUS3 0x1A |
#define QN_TXCH 0x1B |
#define QN_TX_RDSD0 0x1C |
#define QN_TX_RDSD1 0x1D |
#define QN_TX_RDSD2 0x1E |
#define QN_TX_RDSD3 0x1F |
#define QN_TX_RDSD4 0x20 |
#define QN_TX_RDSD5 0x21 |
#define QN_TX_RDSD6 0x22 |
#define QN_TX_RDSD7 0x23 |
#define QN_PAC 0x24 |
#define QN_FDEV 0x25 |
#define QN_RDS 0x26 |
#define QN_GPLT 0x27 |
#define QN_REG_VGA 0x28 |
#define QN_REGISTER_6E 0x6E |
#define QN_REGISTER_49 0x49 |