PU2CLR Si4735 Arduino Library  1.1.9
Arduino Library for Si47XX Devices - By Ricardo Lima Caratti
Receiver Status and Setup

Data Structures

union  si47x_agc_status
 
struct  si47x_agc_status.refined
 
union  si47x_agc_overrride
 
struct  si47x_agc_overrride.arg
 
union  si47x_bandwidth_config
 
struct  si47x_bandwidth_config.param
 
union  si47x_ssb_mode
 
struct  si47x_ssb_mode.param
 
union  si4735_digital_output_format
 Digital audio output format data structure (Property 0x0102. DIGITAL_OUTPUT_FORMAT). More...
 
struct  si4735_digital_output_format.refined
 
struct  si4735_digital_output_sample_rate
 Digital audio output sample structure (Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE). More...
 

Detailed Description


Data Structure Documentation

◆ si47x_agc_status

union si47x_agc_status

Receiver Status and Setup

AGC data types FM / AM and SSB structure to AGC

See also
Si47XX PROGRAMMING GUIDE; AN332; For FM page 80; for AM page 142
AN332 REV 0.8 Universal Programming Guide Amendment for SI4735-D60 SSB and NBFM patches; page 18.
Data Fields
struct si47x_agc_status refined
uint8_t raw[3]

◆ si47x_agc_status.refined

struct si47x_agc_status.refined
Data Fields
uint8_t STCINT: 1
uint8_t DUMMY1: 1
uint8_t RDSINT: 1
uint8_t RSQINT: 1
uint8_t DUMMY2: 2
uint8_t ERR: 1
uint8_t CTS: 1
uint8_t AGCDIS: 1
uint8_t DUMMY: 7
uint8_t AGCIDX

◆ si47x_agc_overrride

union si47x_agc_overrride

If FM, Overrides AGC setting by disabling the AGC and forcing the LNA to have a certain gain that ranges between 0 (minimum attenuation) and 26 (maximum attenuation). If AM, overrides the AGC setting by disabling the AGC and forcing the gain index that ranges between 0

See also
Si47XX PROGRAMMING GUIDE; AN332; For FM page 81; for AM page 143
Data Fields
struct si47x_agc_overrride arg
uint8_t raw[2]

◆ si47x_agc_overrride.arg

struct si47x_agc_overrride.arg
Data Fields
uint8_t AGCDIS: 1
uint8_t DUMMY: 7
uint8_t AGCIDX

◆ si47x_bandwidth_config

union si47x_bandwidth_config

The bandwidth of the AM channel filter data type AMCHFLT values: 0 = 6 kHz Bandwidth
1 = 4 kHz Bandwidth 2 = 3 kHz Bandwidth 3 = 2 kHz Bandwidth 4 = 1 kHz Bandwidth 5 = 1.8 kHz Bandwidth 6 = 2.5 kHz Bandwidth, gradual roll off 7–15 = Reserved (Do not use)

See also
Si47XX PROGRAMMING GUIDE; AN332; pages 125 and 151
Data Fields
struct si47x_bandwidth_config param
uint8_t raw[2]

◆ si47x_bandwidth_config.param

struct si47x_bandwidth_config.param
Data Fields
uint8_t AMCHFLT: 4 Selects the bandwidth of the AM channel filter.
uint8_t DUMMY1: 4
uint8_t AMPLFLT: 1 Enables the AM Power Line Noise Rejection Filter.
uint8_t DUMMY2: 7

◆ si47x_ssb_mode

union si47x_ssb_mode

SSB - datatype for SSB_MODE (property 0x0101)

See also
AN332 REV 0.8 UNIVERSAL PROGRAMMING GUIDE; page 24
Data Fields
struct si47x_ssb_mode param
uint8_t raw[2]

◆ si47x_ssb_mode.param

struct si47x_ssb_mode.param
Data Fields
uint8_t AUDIOBW: 4 0 = 1.2KHz (default); 1=2.2KHz; 2=3KHz; 3=4KHz; 4=500Hz; 5=1KHz
uint8_t SBCUTFLT: 4 SSB side band cutoff filter for band passand low pass filter.
uint8_t AVC_DIVIDER: 4 set 0 for SSB mode; set 3 for SYNC mode;
uint8_t AVCEN: 1 SSB Automatic Volume Control (AVC) enable; 0=disable; 1=enable (default);.
uint8_t SMUTESEL: 1 SSB Soft-mute Based on RSSI or SNR.
uint8_t DUMMY1: 1 Always write 0;.
uint8_t DSP_AFCDIS: 1 0=SYNC MODE, AFC enable; 1=SSB MODE, AFC disable.

◆ si4735_digital_output_format

union si4735_digital_output_format

Digital audio output format data structure (Property 0x0102. DIGITAL_OUTPUT_FORMAT).

Used to configure: DCLK edge, data format, force mono, and sample precision.

See also
Si47XX PROGRAMMING GUIDE; AN332; page 195.
Data Fields
struct si4735_digital_output_format refined
uint16_t raw

◆ si4735_digital_output_format.refined

struct si4735_digital_output_format.refined
Data Fields
uint8_t OSIZE: 2 Digital Output Audio Sample Precision (0=16 bits, 1=20 bits, 2=24 bits, 3=8bits).
uint8_t OMONO: 1 Digital Output Mono Mode (0=Use mono/stereo blend ).
uint8_t OMODE: 4 Digital Output Mode (0000=I2S, 0110 = Left-justified, 1000 = MSB at second DCLK after DFS pulse, 1100 = MSB at first DCLK after DFS pulse).
uint8_t OFALL: 1 Digital Output DCLK Edge (0 = use DCLK rising edge, 1 = use DCLK falling edge)
uint8_t dummy: 8 Always 0.

◆ si4735_digital_output_sample_rate

struct si4735_digital_output_sample_rate

Digital audio output sample structure (Property 0x0104. DIGITAL_OUTPUT_SAMPLE_RATE).

Used to enable digital audio output and to configure the digital audio output sample rate in samples per second (sps).

See also
Si47XX PROGRAMMING GUIDE; AN332; page 196.
Data Fields
uint16_t DOSR