PU2CLR SI470X Arduino Library  1.0.1
Arduino Library for Si470X Devices - By Ricardo Lima Caratti
SI470X.h
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1 
2 /**
3  * @mainpage PU2CLR SI470X Arduino Library
4  * @brief PU2CLR SI470X Arduino Library implementation. <br>
5  * @details This is an Arduino library for the SI4702 and SI4703, BROADCAST RECEIVER.<br>
6  * @details It works with I2C protocol and can provide an easier interface for controlling the SI4702/03 devices.<br>
7  *
8  * This library can be freely distributed using the MIT Free Software model.
9  * Copyright (c) 2020 Ricardo Lima Caratti.
10  * Contact: pu2clr@gmail.com
11  */
12 
13 #include <Arduino.h>
14 #include <Wire.h>
15 
16 
17 #define MAX_DELAY_AFTER_OSCILLATOR 500 // Max delay after the crystal oscilator becomes active
18 
19 
20 #define I2C_DEVICE_ADDR 0x10
21 #define OSCILLATOR_TYPE_CRYSTAL 1 // Crystal
22 #define OSCILLATOR_TYPE_REFCLK 0 // Reference clock
23 
24 #define RDS_STANDARD 0 //!< RDS Mode.
25 #define RDS_VERBOSE 1 //!< RDS Mode.
26 #define SEEK_DOWN 0 //!< Seek Down Direction
27 #define SEEK_UP 1 //!< Seek Up Direction
28 
29 #define FM_BAND_USA_EU 0 //!< 87.5–108 MHz (US / Europe, Default)
30 #define FM_BAND_JAPAN_WIDE 1 //!< 76–108 MHz (Japan wide band)
31 #define FM_BAND_JAPAN 2 //!< 76–90 MHz (Japan)
32 #define FM_BAND_RESERVED 3 //!< Reserved
33 
34 #define REG00 0x00
35 #define REG01 0x01
36 #define REG02 0x02
37 #define REG03 0x03
38 #define REG04 0x04
39 #define REG05 0x05
40 #define REG06 0x06
41 #define REG07 0x07
42 #define REG08 0x08
43 #define REG09 0x09
44 #define REG0A 0x0A
45 #define REG0B 0x0B
46 #define REG0C 0x0C
47 #define REG0D 0x0D
48 #define REG0E 0x0E
49 #define REG0F 0x0F
50 
51 /**
52  * @defgroup GA01 Union, Structure and Defined Data Types
53  * @brief SI470X Defined Data Types
54  * @details Defined Data Types is a way to represent the SI470X registers information
55  * @details Some information appears to be inaccurate due to translation problems from Chinese to English.
56  * @details The information shown here was extracted from Datasheet:
57  * @details SI470X stereo FM digital tuning radio documentation.
58  * @details Other information seems incomplete even in the original Chinese Datasheet.
59  * @details For example: Reg 10 (0x0A). There is no information about it. The Reg11 and 12 seem wrong
60  */
61 
62 /**
63  * @ingroup GA01
64  * @brief Device ID
65  *
66  */
67 typedef union {
68  struct {
69  uint16_t MFGID : 12; //!< Manufacturer ID.
70  uint16_t PN: 4; //!< Part Number.
71  } refined;
73 } si470x_reg00;
74 
75 /**
76  * @ingroup GA01
77  * @brief Chip ID
78  *
79  */
80 typedef union {
81  struct
82  {
83  uint16_t FIRMWARE : 6; //!< Firmware Version.
84  uint16_t DEV : 4; //!< 0 before powerup; 0001 after powerup = Si4702; 1000 before powerup = Si4703; 1001 after powerup = Si4703.
85  uint16_t REV : 6; //!< Chip Version; 0x04 = Rev C
86  } refined;
88 } si470x_reg01;
89 
90 /**
91  * @ingroup GA01
92  * @brief Power Configuratio
93  *
94  */
95 typedef union {
96  struct
97  {
98  uint8_t ENABLE : 1; //!< Powerup Enable; Refer to “4.9. Reset, Powerup, and Powerdown”; Default = 0.
99  uint8_t RESERVED1 : 5; //!< Reserved; Always write to 0.
100  uint8_t DISABLE : 1; //!< Powerup Disable; Refer to “4.9. Reset, Powerup, and Powerdown”; Default = 0.
101  uint8_t RESERVED2 : 1; //!< Reserved; Always write to 0.
102  uint8_t SEEK : 1; //!< 0 = Disable (default); 1 = Enable;
103  uint8_t SEEKUP : 1; //!< Seek Direction; 0 = Seek down (default); 1 = Seek up.
104  uint8_t SKMODE : 1; //!< Seek Mode; 0 = Wrap at the upper or lower band limit and continue seeking (default); 1 = Stop seeking at the upper or lower band limit.
105  uint8_t RDSM : 1; //!< RDS Mode; 0 = Standard (default); 1 = Verbose; Refer to “4.4. RDS/RBDS Processor and Functionality”.
106  uint8_t RESERVED3 : 1; //!< Reserved; Always write to 0.
107  uint8_t MONO : 1; //!< Mono Select; 0 = Stereo (default); 1 = Force mono.
108  uint8_t DMUTE : 1; //!< Mute Disable; 0 = Mute enable (default); 1 = Mute disable.
109  uint8_t DSMUTE : 1; //!< Softmute Disable; 0 = Softmute enable (default); 1 = Softmute disable.
110  } refined;
112 } si470x_reg02;
113 
114 /**
115  * @ingroup GA01
116  * @brief Channe
117  * @details Channel value for tune operation. If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.
118  * @details If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
119  * @details CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the current tuned channel and is updated during a seek operation and after a seek or tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].
120  * @details The tune operation begins when the TUNE bit is set high. The STC bit is set high when the tune operation completes. The STC bit must be set low by setting the TUNE bit low before the next tune or seek may begin.
121  */
122 typedef union {
123  struct
124  {
125  uint16_t CHAN : 10; //!< Channel Select;
126  uint16_t RESERVED : 5; //!< Reserved; Always write to 0;
127  uint16_t TUNE : 1; //!< Tune. 0 = Disable (default); 1 = Enable.
128  } refined;
130 } si470x_reg03;
131 
132 /**
133  * @ingroup GA01
134  * @brief System Configuration 1
135  * @details Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the STC 0Ah[14] bit is set.
136  * @details Setting RDSIEN = 1 will generate a 5 ms low pulse on GPIO2 when the RDSR 0Ah[15] bit is set.
137  * @details Setting STCIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when the STC 0Ah[14] bit is set.
138  * | BLNDADJ value | Description |
139  * | ------------ | ----------- |
140  * | 0 | 31–49 RSSI dBμV (default) |
141  * | 1 | 37–55 RSSI dBμV (+6 dB) |
142  * | 2 | 19–37 RSSI dBμV (–12 dB) |
143  * | 3 | 25–43 RSSI dBμV (–6 dB) |
144  *
145  */
146 typedef union {
147  struct
148  {
149  uint8_t GPIO1 : 2; //!< General Purpose I/O 1; 00 = High impedance (default); 01 = Reserved; 10 = Low; 11 = High.
150  uint8_t GPIO2 : 2; //!< General Purpose I/O 2. 00 = High impedance (default); 01 = Reserved; 10 = Low; 11 = High.
151  uint8_t GPIO3 : 2; //!< General Purpose I/O 2. 00 = High impedance (default); 01 = Reserved; 10 = Low; 11 = High.
152  uint8_t BLNDADJ : 2; //!< Stereo/Mono Blend Level Adjustment. Sets the RSSI range for stereo/mono blend. See table above.
153  uint8_t RESERVED1 : 2; //!< Reserved; Always write to 0.
154  uint8_t AGCD : 1; //!< AGC Disable; 0 = AGC enable (default); 1 = AGC disable.
155  uint8_t DE : 1; //!< De-emphasis; 0 = 75 μs. Used in USA (default); 1 = 50 μs. Used in Europe, Australia, Japan.
156  uint8_t RDS : 1; //!< RDS Enable; 0 = Disable (default); 1 = Enable.
157  uint8_t RESERVED2 : 1; //!< Reserved; Always write to 0.
158  uint8_t STCIEN : 1; //!< Seek/Tune Complete Interrupt Enable; 0 = Disable Interrupt (default); 1 = Enable Interrupt.
159  uint8_t RDSIEN : 1; //!< RDS Interrupt Enable; 0 = Disable Interrupt (default); 1 = Enable Interrupt.
160  } refined;
162 } si470x_reg04;
163 
164 /**
165  * @ingroup GA01
166  * @brief System Configuration 2
167  * @details SEEKTH presents the logarithmic RSSI threshold for the seek operation. The Si4702/03-C19 will not validate channels with RSSI below the SEEKTH value. SEEKTH is one of multiple parameters that can be used to validate channels. For more information, see "AN284: Si4700/01 Firmware 15 Seek Adjustability and Set- tings."
168  *
169  * | BAND value | Description |
170  * | ---------- | ----------- |
171  * | 0 | 00 = 87.5–108 MHz (USA, Europe) (Default) |
172  * | 1 | 01 = 76–108 MHz (Japan wide band) |
173  * | 2 | 10 = 76–90 MHz (Japan) |
174  * | 3 | 11 = Reserved |
175  */
176 typedef union {
177  struct
178  {
179  uint8_t VOLUME : 4; //!< Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit; 0000 = mute (default);
180  uint8_t SPACE : 2; //!< Channel Spacing; 00 = 200 kHz (USA, Australia) (default); 01 = 100 kHz (Europe, Japan); 10 = 50 kHz.
181  uint8_t BAND : 2; //!< Band Select. See table above.
182  uint8_t SEEKTH; //!< RSSI Seek Threshold. 0x00 = min RSSI (default); 0x7F = max RSSI.
183  } refined;
185 } si470x_reg05;
186 
187 /**
188  * @ingroup GA01
189  * @brief System Configuration 3
190  * @details The VOLEXT bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings adjust the volume between 0 and –28 dBFS. With the bit set to 1, the 15 volume set- tings adjust the volume between –30 and –58 dBFS.
191  * @details Refer to 4.5. "Stereo Audio Processing" on page 16.
192  *
193  * | Softmute Attenuation | Description |
194  * | 0 | 16 dB (default) |
195  * | 1 | 14 dB |
196  * | 2 | 12 dB |
197  * | 3 | 10 dB |
198  *
199  * | Softmute Attack/Recover Rate | Description |
200  * | 0 | fastest (default) |
201  * | 1 | fast |
202  * | 2 | slow |
203  * | 3 | slowest |
204  *
205  */
206 typedef union {
207  struct
208  {
209  uint8_t SKCNT : 4; //!< Seek FM Impulse Detection Threshold; 0000 = disabled (default); 0001 = max (most stops); 1111 = min (fewest stops). Allowable number of FM impulses for a valid seek channel.
210  uint8_t SKSNR : 4; //!< Seek SNR Threshold; 0000 = disabled (default); 0001 = min (most stops); 0111 = max (fewest stops); Required channel SNR for a valid seek channel.
211  uint8_t VOLEXT : 1; //!< Extended Volume Range; 0 = disabled (default); 1 = enabled.
212  uint8_t RESERVED : 3; //!< Reserved; Always write to zero.
213  uint8_t SMUTEA : 2; //!< Softmute Attenuation; See table above.
214  uint8_t SMUTER : 2; //!< Softmute Attack/Recover Rate; See table above
215  } refined;
217 } si470x_reg06;
218 
219 /**
220  * @ingroup GA01
221  * @brief Test 1
222  * @details Setting AHIZEN maintains a dc bias of 0.5 x VIO on the LOUT and ROUT pins to pre- vent the ESD diodes from clamping to the VIO or GND rail in response to the output swing of another device.
223  * @details Register 07h containing the AHIZEN bit must not be written during the powerup sequence and high-Z only takes effect when in powerdown and VIO is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in pow- erdown and as 0x3C04 while in powerup.
224  * @details The internal crystal oscillator requires an external 32.768 kHz crystal as shown in "Typical Application Schematic" on page 14.
225  * @details The oscillator must be enabled before powerup (ENABLE = 1) as shown in Figure 9, “Initialization Sequence,” on page 21. It should only be disabled after powerdown (ENABLE = 0).
226  * @details Bits 13:0 of register 07h must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup. Refer to Si4702/03 Internal Crystal Oscillator Errata.
227  */
228 typedef union {
229  struct
230  {
231  uint16_t RESERVED : 14; //!< Reserved; If written, these bits should be read first and then written with their pre-existing val- ues. Do not write during powerup.
232  uint16_t AHIZEN : 1; //!< Audio High-Z Enable; 0 = Disable (default); 1 = Enable.
233  uint16_t XOSCEN : 1; //!< Crystal Oscillator Enable; 0 = Disable (default); 1 = Enable.
234  } refined;
236 } si470x_reg07;
237 
238 /**
239  * @ingroup GA01
240  * @brief Test 2
241  * @details If written, these bits should be read first and then written with their pre-existing val- ues. Do not write during powerup.
242  */
243 typedef union {
244  struct
245  {
246  uint8_t lowByte; //!< Reserved
247  uint8_t highByte; //!< Reserved
248  } refined;
250 } si470x_reg08;
251 
252 /**
253  * @ingroup GA01
254  * @brief Boot Configuration
255  * @details If written, these bits should be read first and then written with their pre-existing val- ues. Do not write during powerup.
256  */
257 typedef union {
258  struct
259  {
260  uint8_t lowByte; //!< Reserved
261  uint8_t highByte; //!< Reserved
262  } refined;
264 } si470x_reg09;
265 
266 /**
267  * @ingroup GA01
268  * @brief Status RSSI
269  * @details RSSI is measured units of dBμV in 1 dB increments with a maximum of approximately 75 dBμV. Si4702/03-C19 does not report RSSI levels greater than 75 dBuV.
270  * @details AFCRL is updated after a tune or seek operation completes and indicates a valid or invalid channel. During normal operation, AFCRL is updated to reflect changing RF envi- ronments.
271  * @details The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to find a channel qualified as valid according to the seek parameters.
272  * @details The SF/BL flag is set high when SKMODE 02h[10] = 1 and the upper or lower band limit has been reached. The SEEK 02h[8] bit must be set low to clear SF/BL.
273  * @details The seek/tune complete flag is set when the seek or tune operation completes. Setting the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.
274  *
275  * | RDS Block A Errors | Description |
276  * | ------------------ | ----------- |
277  * | 0 | 0 errors requiring correction |
278  * | 1 | 1–2 errors requiring correction |
279  * | 2 | 3–5 errors requiring correction |
280  * | 3 | 6+ errors or error in checkword, correction not possible |
281  *
282  */
283 typedef union {
284  struct
285  {
286  uint8_t RSSI; //!< RSSI (Received Signal Strength Indicator).
287  uint8_t ST : 1; //!< Stereo Indicator; 0 = Mono; 1 = Stereo.
288  uint8_t BLERA : 2; //!< RDS Block A Errors; See table above.
289  uint8_t RDSS : 1; //!< RDS Synchronized; 0 = RDS decoder not synchronized (default); 1 = RDS decoder synchronized.
290  uint8_t AFCRL : 1; //!< AFC Rail; 0 = AFC not railed; 1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.
291  uint8_t SF_BL : 1; //!< Seek Fail/Band Limit; 0 = Seek successful; 1 = Seek failure/Band limit reached.
292  uint8_t STC : 1; //!< Seek/Tune Complete; 0 = Not complete (default); 1 = Complete.
293  uint8_t RDSR : 1; //!< RDS Ready; 0 = No RDS group ready (default); 1 = New RDS group ready.
294  } refined;
296 } si470x_reg0a;
297 
298 /**
299  * @ingroup GA01
300  * @brief Read Channel
301  * @details If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz. If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
302  * @details READCHAN[9:0] provides the current tuned channel and is updated during a seek operation and after a seek or tune operation completes. Spacing and channel are set with the bits SPACE 05h[5:4] and CHAN 03h[9:0].
303  *
304  * | RDS block Errors | Description |
305  * | -----------------| ----------- |
306  * | 0 | 0 errors requiring correction |
307  * | 1 | 1–2 errors requiring correction |
308  * | 2 | 3–5 errors requiring correction |
309  * | 3 | 6+ errors or error in checkword, correction not possible |
310  *
311  */
312 typedef union {
313  struct
314  {
315  uint16_t READCHAN : 10; //!< Read Channel.
316  uint16_t BLERD : 2; //!< RDS Block D Errors. See table above.
317  uint16_t BLERC : 2; //!< RDS Block C Errors. See table above.
318  uint16_t BLERB : 2; //!< RDS Block B Errors. See table above.
319  } refined;
321 } si470x_reg0b;
322 
323 /**
324  * @ingroup GA01
325  * @brief RDS Block A
326  *
327  */
328 typedef uint16_t si470x_reg0c; //!< RDS Block A Data.
329 
330 /**
331  * @ingroup GA01
332  * @brief RDS Block B
333  *
334  */
335 typedef uint16_t si470x_reg0d; //!< RDS Block B Data.
336 
337 /**
338  * @ingroup GA01
339  * @brief RDS Block C
340  *
341  */
342 typedef uint16_t si470x_reg0e; //!< RDS Block C Data.
343 
344 /**
345  * @ingroup GA01
346  * @brief RDS Block D
347  *
348  */
349 typedef uint16_t si470x_reg0f; //!< RDS Block D Data.
350 
351 /**
352  * @ingroup GA01
353  * @brief RDS Block B data type
354  *
355  * @details For GCC on System-V ABI on 386-compatible (32-bit processors), the following stands:
356  *
357  * 1) Bit-fields are allocated from right to left (least to most significant).
358  * 2) A bit-field must entirely reside in a storage unit appropriate for its declared type.
359  * Thus a bit-field never crosses its unit boundary.
360  * 3) Bit-fields may share a storage unit with other struct/union members, including members that are not bit-fields.
361  * Of course, struct members occupy different parts of the storage unit.
362  * 4) Unnamed bit-fields' types do not affect the alignment of a structure or union, although individual
363  * bit-fields' member offsets obey the alignment constraints.
364  *
365  * @see also https://en.wikipedia.org/wiki/Radio_Data_System
366  */
367 typedef union {
368  struct
369  {
370  uint8_t address : 2; // Depends on Group Type and Version codes. If 0A or 0B it is the Text Segment Address.
371  uint8_t DI : 1; // Decoder Controll bit
372  uint8_t MS : 1; // Music/Speech
373  uint8_t TA : 1; // Traffic Announcement
374  uint8_t programType : 5; // PTY (Program Type) code
375  uint8_t trafficProgramCode : 1; // (TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
376  uint8_t versionCode : 1; // (B0) => 0=A; 1=B
377  uint8_t groupType : 4; // Group Type code.
378  } group0;
379  struct
380  {
381  uint8_t address : 4; // Depends on Group Type and Version codes. If 2A or 2B it is the Text Segment Address.
382  uint8_t textABFlag : 1; // Do something if it chanhes from binary "0" to binary "1" or vice-versa
383  uint8_t programType : 5; // PTY (Program Type) code
384  uint8_t trafficProgramCode : 1; // (TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
385  uint8_t versionCode : 1; // (B0) => 0=A; 1=B
386  uint8_t groupType : 4; // Group Type code.
387  } group2;
388  struct
389  {
390  uint8_t content : 4; // Depends on Group Type and Version codes.
391  uint8_t textABFlag : 1; // Do something if it chanhes from binary "0" to binary "1" or vice-versa
392  uint8_t programType : 5; // PTY (Program Type) code
393  uint8_t trafficProgramCode : 1; // (TP) => 0 = No Traffic Alerts; 1 = Station gives Traffic Alerts
394  uint8_t versionCode : 1; // (B0) => 0=A; 1=B
395  uint8_t groupType : 4; // Group Type code.
396  } refined;
398 } si47x_rds_blockb;
399 
400 /**
401  * @ingroup GA01
402  * Group RDS type 4A ( RDS Date and Time)
403  * When group type 4A is used by the station, it shall be transmitted every minute according to EN 50067.
404  * This Structure uses blocks 2,3 and 5 (B,C,D)
405  *
406  * ATTENTION:
407  * To make it compatible with 8, 16 and 32 bits platforms and avoid Crosses boundary, it was necessary to
408  * split minute and hour representation.
409  */
410 typedef union {
411  struct
412  {
413  uint8_t offset : 5; // Local Time Offset
414  uint8_t offset_sense : 1; // Local Offset Sign ( 0 = + , 1 = - )
415  uint8_t minute1 : 2; // UTC Minutes - 2 bits less significant (void “Crosses boundary”).
416  uint8_t minute2 : 4; // UTC Minutes - 4 bits more significant (void “Crosses boundary”)
417  uint8_t hour1 : 4; // UTC Hours - 4 bits less significant (void “Crosses boundary”)
418  uint8_t hour2 : 1; // UTC Hours - 4 bits more significant (void “Crosses boundary”)
419  uint32_t mjd : 17; // Modified Julian Day Code
420  } refined;
422 } si47x_rds_date_time;
423 
424 /**
425  * @ingroup GA01
426  * @brief Converts 16 bits word to two bytes
427  */
428 typedef union {
429  struct
430  {
431  uint8_t lowByte;
432  uint8_t highByte;
433  } refined;
435 } word16_to_bytes;
436 
437 /**
438  * @ingroup GA01
439  * @brief KT0915 Class
440  * @details This class implements all functions that will help you to control the KT0915 devices.
441  *
442  * @author PU2CLR - Ricardo Lima Caratti
443  */
444 class SI470X {
445 
446  private:
447  uint16_t shadowRegisters[17]; //!< shadow registers
448 
449  // Device registers map - References to the shadow registers
450  si470x_reg00 *reg00 = (si470x_reg00 *)&shadowRegisters[REG00];
451  si470x_reg01 *reg01 = (si470x_reg01 *)&shadowRegisters[REG01];
452  si470x_reg02 *reg02 = (si470x_reg02 *)&shadowRegisters[REG02];
453  si470x_reg03 *reg03 = (si470x_reg03 *)&shadowRegisters[REG03];
454  si470x_reg04 *reg04 = (si470x_reg04 *)&shadowRegisters[REG04];
455  si470x_reg05 *reg05 = (si470x_reg05 *)&shadowRegisters[REG05];
456  si470x_reg06 *reg06 = (si470x_reg06 *)&shadowRegisters[REG06];
457  si470x_reg07 *reg07 = (si470x_reg07 *)&shadowRegisters[REG07];
458  si470x_reg08 *reg08 = (si470x_reg08 *)&shadowRegisters[REG08];
459  si470x_reg09 *reg09 = (si470x_reg09 *)&shadowRegisters[REG09];
460  si470x_reg0a *reg0a = (si470x_reg0a *)&shadowRegisters[REG0A];
461  si470x_reg0b *reg0b = (si470x_reg0b *)&shadowRegisters[REG0B];
462  si470x_reg0c *reg0c = (si470x_reg0c *)&shadowRegisters[REG0C];
463  si470x_reg0d *reg0d = (si470x_reg0d *)&shadowRegisters[REG0D];
464  si470x_reg0e *reg0e = (si470x_reg0e *)&shadowRegisters[REG0E];
465  si470x_reg0f *reg0f = (si470x_reg0f *)&shadowRegisters[REG0F];
466 
467  uint16_t startBand[4] = {8750, 7600, 7600, 6400 };
468  uint16_t fmSpace[4] = {20, 10, 5, 1};
469 
470  protected:
472  int resetPin;
477  int rdsInterruptPin = -1;
481 
482  public :
483 
484  /**
485  * @brief Set the Delay After Crystal On (default 500ms)
486  *
487  * @param ms_value Value in milliseconds
488  */
489  inline void setDelayAfterCrystalOn(uint8_t ms_value) { maxDelayAftarCrystalOn = ms_value; };
490 
491  void getAllRegisters();
492  void setAllRegisters(uint8_t limit = 0x07);
493  void getStatus();
494  void waitAndFinishTune();
495 
496  void reset();
497 
498  void powerUp();
499  void powerDown();
500 
501  void setup(int resetPin, int rdsInterruptPin = -1, int seekInterruptPin = -1, uint8_t oscillator_type = OSCILLATOR_TYPE_CRYSTAL);
502  void setup(int resetPin, uint8_t oscillator_type);
503 
504  void setFrequency(uint16_t frequency);
508  void setChannel(uint16_t channel);
509  void seek(uint8_t seek_mode, uint8_t direction);
510 
511  void setBand(uint8_t band = 1);
512  void setSpace(uint8_t space = 0);
513  int getRssi();
514  void setSoftmute(bool value);
515  void setMute(bool value);
516  void setMono(bool value);
517  void setRdsMode(uint8_t rds_mode = 0);
518 
524 
525  void setVolume(uint8_t value);
526  uint8_t getVolume();
527  void setVolumeUp();
528  void setVolumeDown();
529 
530 
531 
532 
533 };
si470x_reg02::raw
uint16_t raw
Definition: SI470X.h:111
REG01
#define REG01
Definition: SI470X.h:35
si470x_reg01::raw
uint16_t raw
Definition: SI470X.h:87
REG05
#define REG05
Definition: SI470X.h:39
si47x_rds_blockb::blockB
si470x_reg0d blockB
Definition: SI470X.h:397
SI470X::getFrequency
uint16_t getFrequency()
Gets the current frequency.
Definition: SI470X.cpp:265
SI470X::setSoftmute
void setSoftmute(bool value)
Sets the Softmute true or false.
Definition: SI470X.cpp:370
REG0F
#define REG0F
Definition: SI470X.h:49
SI470X::setup
void setup(int resetPin, int rdsInterruptPin=-1, int seekInterruptPin=-1, uint8_t oscillator_type=OSCILLATOR_TYPE_CRYSTAL)
Starts the device.
Definition: SI470X.cpp:204
I2C_DEVICE_ADDR
#define I2C_DEVICE_ADDR
Definition: SI470X.h:20
SI470X::rdsInterruptPin
int rdsInterruptPin
Definition: SI470X.h:477
SI470X::getDeviceId
uint8_t getDeviceId()
Gets the Device identification.
Definition: SI470X.cpp:502
SI470X::maxDelayAftarCrystalOn
uint16_t maxDelayAftarCrystalOn
Definition: SI470X.h:480
REG00
#define REG00
Definition: SI470X.h:34
SI470X::getManufacturerId
uint16_t getManufacturerId()
Gets the Manufacturer ID.
Definition: SI470X.cpp:481
SI470X::deviceAddress
int deviceAddress
Definition: SI470X.h:471
SI470X::setRdsMode
void setRdsMode(uint8_t rds_mode=0)
Sets the Rds Mode Standard or Verbose.
Definition: SI470X.cpp:406
SI470X::seek
void seek(uint8_t seek_mode, uint8_t direction)
Seek function.
Definition: SI470X.cpp:305
word16_to_bytes::raw
uint16_t raw
Definition: SI470X.h:434
SI470X::getAllRegisters
void getAllRegisters()
PU2CLR SI470X Arduino Library.
Definition: SI470X.cpp:27
REG09
#define REG09
Definition: SI470X.h:43
REG0C
#define REG0C
Definition: SI470X.h:46
SI470X::resetPin
int resetPin
Definition: SI470X.h:472
si470x_reg08::raw
uint16_t raw
Definition: SI470X.h:249
SI470X::waitAndFinishTune
void waitAndFinishTune()
Wait STC (Seek/Tune Complete) status becomes 0.
Definition: SI470X.cpp:97
SI470X::getRealChannel
uint16_t getRealChannel()
Gets the current channel stored in register 0x0B.
Definition: SI470X.cpp:276
si470x_reg06::raw
uint16_t raw
Definition: SI470X.h:216
SI470X::powerUp
void powerUp()
Powers the receiver on.
Definition: SI470X.cpp:132
SI470X::currentFMBand
uint8_t currentFMBand
Definition: SI470X.h:474
si470x_reg05::raw
uint16_t raw
Definition: SI470X.h:184
REG03
#define REG03
Definition: SI470X.h:37
si470x_reg07::raw
uint16_t raw
Definition: SI470X.h:235
si47x_rds_date_time::raw
uint8_t raw[6]
Definition: SI470X.h:421
SI470X::getRssi
int getRssi()
Gets the Rssi.
Definition: SI470X.cpp:359
REG04
#define REG04
Definition: SI470X.h:38
SI470X::setDelayAfterCrystalOn
void setDelayAfterCrystalOn(uint8_t ms_value)
Set the Delay After Crystal On (default 500ms)
Definition: SI470X.h:489
SI470X::powerDown
void powerDown()
Powers the receiver off.
Definition: SI470X.cpp:183
si470x_reg0c
uint16_t si470x_reg0c
RDS Block A.
Definition: SI470X.h:328
SI470X::currentFMSpace
uint8_t currentFMSpace
Definition: SI470X.h:475
SI470X::setAllRegisters
void setAllRegisters(uint8_t limit=0x07)
Sets values to the device registers from 0x02 to 0x07.
Definition: SI470X.cpp:61
REG02
#define REG02
Definition: SI470X.h:36
SI470X::setVolume
void setVolume(uint8_t value)
Sets the audio volume level.
Definition: SI470X.cpp:418
REG0D
#define REG0D
Definition: SI470X.h:47
SI470X::currentFrequency
uint16_t currentFrequency
Definition: SI470X.h:473
si470x_reg09::raw
uint16_t raw
Definition: SI470X.h:263
SI470X::setBand
void setBand(uint8_t band=1)
Sets the FM Band
Definition: SI470X.cpp:330
OSCILLATOR_TYPE_CRYSTAL
#define OSCILLATOR_TYPE_CRYSTAL
Definition: SI470X.h:21
SI470X::seekInterruptPin
int seekInterruptPin
Definition: SI470X.h:478
SI470X::getStatus
void getStatus()
Gets the value of the 0x0A register.
Definition: SI470X.cpp:80
REG07
#define REG07
Definition: SI470X.h:41
SI470X::reset
void reset()
Resets the device.
Definition: SI470X.cpp:118
SI470X::setMute
void setMute(bool value)
Sets the Mute true or false.
Definition: SI470X.cpp:382
REG08
#define REG08
Definition: SI470X.h:42
MAX_DELAY_AFTER_OSCILLATOR
#define MAX_DELAY_AFTER_OSCILLATOR
Definition: SI470X.h:17
SI470X::setChannel
void setChannel(uint16_t channel)
Sets the channel.
Definition: SI470X.cpp:238
SI470X::getChipVersion
uint8_t getChipVersion()
Gets the Chip Version.
Definition: SI470X.cpp:512
si470x_reg0a::raw
uint16_t raw
Definition: SI470X.h:295
SI470X::currentVolume
uint8_t currentVolume
Definition: SI470X.h:476
si470x_reg0e
uint16_t si470x_reg0e
RDS Block C.
Definition: SI470X.h:342
SI470X::setMono
void setMono(bool value)
Sets the Mono true or false (stereo)
Definition: SI470X.cpp:394
REG06
#define REG06
Definition: SI470X.h:40
SI470X::setVolumeUp
void setVolumeUp()
Increments the audio volume.
Definition: SI470X.cpp:442
SI470X::setup
void setup(int resetPin, uint8_t oscillator_type)
Starts the device.
Definition: SI470X.cpp:228
si470x_reg0f
uint16_t si470x_reg0f
RDS Block D.
Definition: SI470X.h:349
si470x_reg0b::raw
uint16_t raw
Definition: SI470X.h:320
SI470X::getFirmwareVersion
uint8_t getFirmwareVersion()
Gets the Firmware Version.
Definition: SI470X.cpp:492
REG0E
#define REG0E
Definition: SI470X.h:48
si470x_reg03::raw
uint16_t raw
Definition: SI470X.h:129
si470x_reg04::raw
uint16_t raw
Definition: SI470X.h:161
REG0A
#define REG0A
Definition: SI470X.h:44
SI470X::getVolume
uint8_t getVolume()
Gets the current audio volume level.
Definition: SI470X.cpp:432
si470x_reg00::raw
uint16_t raw
Definition: SI470X.h:72
SI470X::setVolumeDown
void setVolumeDown()
Decrements the audio volume.
Definition: SI470X.cpp:456
SI470X::oscillatorType
int oscillatorType
Definition: SI470X.h:479
SI470X::setSpace
void setSpace(uint8_t space=0)
Sets the FM Space
Definition: SI470X.cpp:347
SI470X::getRealFrequency
uint16_t getRealFrequency()
Gets the frequency based on READCHAN register (0x0B)
Definition: SI470X.cpp:289
REG0B
#define REG0B
Definition: SI470X.h:45
SI470X::getPartNumber
uint8_t getPartNumber()
Gets the Part Number.
Definition: SI470X.cpp:471
SI470X::setFrequency
void setFrequency(uint16_t frequency)
Sets the frequency.
Definition: SI470X.cpp:252
si470x_reg0d
uint16_t si470x_reg0d
RDS Block B.
Definition: SI470X.h:335