FabGL
ESP32 Display Controller and Graphics Library
ulp_macro_ex.h
1 #pragma once
2 
3 
4 
5 #include "esp_attr.h"
6 #include "esp_err.h"
7 #include "esp_log.h"
8 #include "esp32/ulp.h"
9 
10 #include "soc/soc.h"
11 #include "soc/rtc_cntl_reg.h"
12 #include "soc/sens_reg.h"
13 
14 
16 // Support for missing macros for operations on STAGE register
17 // fabgl changes:
18 
19 #define ALU_SEL_STAGE_INC 0
20 #define ALU_SEL_STAGE_DEC 1
21 #define ALU_SEL_STAGE_RST 2
22 
23 #define SUB_OPCODE_STAGEB 2
24 
25 // Increment stage register by immediate value (8 bit)
26 #define I_STAGEINCI(imm_) { .alu_imm = { \
27  .dreg = 0, \
28  .sreg = 0, \
29  .imm = imm_, \
30  .unused = 0, \
31  .sel = ALU_SEL_STAGE_INC, \
32  .sub_opcode = SUB_OPCODE_ALU_CNT, \
33  .opcode = OPCODE_ALU } }
34 
35 // Decrement stage register by immediate value (8 bit)
36 #define I_STAGEDECI(imm_) { .alu_imm = { \
37  .dreg = 0, \
38  .sreg = 0, \
39  .imm = imm_, \
40  .unused = 0, \
41  .sel = ALU_SEL_STAGE_DEC, \
42  .sub_opcode = SUB_OPCODE_ALU_CNT, \
43  .opcode = OPCODE_ALU } }
44 
45 // Reset stage register to zero
46 #define I_STAGERSTI() { .alu_imm = { \
47  .dreg = 0, \
48  .sreg = 0, \
49  .imm = 0, \
50  .unused = 0, \
51  .sel = ALU_SEL_STAGE_RST, \
52  .sub_opcode = SUB_OPCODE_ALU_CNT, \
53  .opcode = OPCODE_ALU } }
54 
55 // Branch relative if STAGE less than immediate value (8 bit)
56 #define I_STAGEBL(pc_offset, imm_value) { .b = { \
57  .imm = imm_value, \
58  .cmp = 0, \
59  .offset = abs(pc_offset), \
60  .sign = (pc_offset >= 0) ? 0 : 1, \
61  .sub_opcode = SUB_OPCODE_STAGEB, \
62  .opcode = OPCODE_BRANCH } }
63 
64 // Branch relative if STAGE less or equal than immediate value (8 bit)
65 #define I_STAGEBLE(pc_offset, imm_value) { .b = { \
66  .imm = imm_value, \
67  .cmp = 1, \
68  .offset = abs(pc_offset), \
69  .sign = (pc_offset >= 0) ? 0 : 1, \
70  .sub_opcode = SUB_OPCODE_STAGEB, \
71  .opcode = OPCODE_BRANCH } }
72 
73 // Branch relative if STAGE greater or equal than immediate value (8 bit)
74 #define I_STAGEBGE(pc_offset, imm_value) { .b = { \
75  .imm = 0x8000 | imm_value, \
76  .cmp = 0, \
77  .offset = abs(pc_offset), \
78  .sign = (pc_offset >= 0) ? 0 : 1, \
79  .sub_opcode = SUB_OPCODE_STAGEB, \
80  .opcode = OPCODE_BRANCH } }
81 
82 // STAGE register branches to labels.
83 
84 #define M_STAGEBL(label_num, imm_value) \
85  M_BRANCH(label_num), \
86  I_STAGEBL(0, imm_value)
87 
88 #define M_STAGEBGE(label_num, imm_value) \
89  M_BRANCH(label_num), \
90  I_STAGEBGE(0, imm_value)
91 
92 #define M_STAGEBLE(label_num, imm_value) \
93  M_BRANCH(label_num), \
94  I_STAGEBLE(0, imm_value)
95 
97 
98 
99 
100 esp_err_t ulp_process_macros_and_load_ex(uint32_t load_addr, const ulp_insn_t* program, size_t* psize);