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Macros
#define	WHO_AM_I 0x00 /* WHO_AM_I[7:0] */
#define	WHO_AM_I_VAL 0xEA
#define	USER_CTRL 0x03 /* DMP_EN FIFO_EN I2C_MST_EN I2C_IF_DIS DMP_RST SRAM_RST I2C_MST_RST - */
#define	USER_CTRL_DMP_EN BIT(7)
#define	USER_CTRL_FIFO_EN BIT(6)
#define	USER_CTRL_I2C_MST_EN BIT(5)
#define	USER_CTRL_I2C_IF_DIS BIT(4)
#define	USER_CTRL_DMP_RST BIT(3)
#define	USER_CTRL_SRAM_RST BIT(2)
#define	USER_CTRL_I2C_MST_RST BIT(1)
#define	LP_CONFIG 0x05 /* I2C_MST_CYCLE ACCEL_CYCLE GYRO_CYCLE - */
#define	LP_I2C_MST_CYCLE BIT(6)
#define	LP_ACCEL_CYCLE BIT(5)
#define	LP_GYRO_CYCLE BIT(4)
#define	PWR_MGMT_1 0x06 /* DEVICE_RESET SLEEP LP_EN - TEMP_DIS CLKSEL[2:0] */
#define	PWR_DEVICE_RESET BIT(7)
#define	PWR_SLEEP BIT(6)
#define	PWR_LP_EN BIT(5)
#define	PWR_TEMP_DIS BIT(3)
#define	PWR_CLKSEL_MASK 0x07
#define	PWR_CLKSEL_INT_20MHZ 0x01
#define	PWR_CLKSEL_AUTO 0x01 /* typical: auto selects best source */
#define	PWR_MGMT_2 0x07 /* - DISABLE_ACCEL DISABLE_GYRO */
#define	PWR_DISABLE_ACCEL BIT(3)
#define	PWR_DISABLE_GYRO BIT(0)
#define	INT_PIN_CFG 0x0F /* INT1_ACTL INT1_OPEN INT1_LATCH_INT_EN INT_ANYRD_2CLEAR ACTL_FSYNC FSYNC_INT_MODE_EN BYPASS_EN - */
#define	INT1_ACTL BIT(7) /* active low */
#define	INT1_OPEN BIT(6) /* open-drain */
#define	INT1_LATCH_INT_EN BIT(5) /* latch until status read */
#define	INT_ANYRD_2CLEAR BIT(4)
#define	INT_ACTL_FSYNC BIT(3)
#define	FSYNC_INT_MODE_EN BIT(2)
#define	BYPASS_EN BIT(1) /* I2C bypass to aux devices */
#define	INT_ENABLE 0x10 /* REG_WOF_EN - WOM_INT_EN PLL_RDY_EN DMP_INT1_EN I2C_MST_INT_EN */
#define	INT_REG_WOF_EN BIT(7)
#define	INT_WOM_INT_EN BIT(3)
#define	INT_PLL_RDY_EN BIT(2)
#define	INT_DMP_INT1_EN BIT(1)
#define	INT_I2C_MST_INT_EN BIT(0)
#define	INT_ENABLE_1 0x11 /* RAW_DATA_0_RDY_EN */
#define	INT_RAW_DATA_0_RDY_EN BIT(0)
#define	INT_ENABLE_2 0x12 /* FIFO_OVERFLOW_EN[4:0] */
#define	INT_ENABLE_3 0x13 /* FIFO_WM_EN[4:0] */
#define	I2C_MST_STATUS 0x17 /* PASS_THROUGH, _DONE, _NACK, LOST_ARB */
#define	MST_PASS_THROUGH BIT(7)
#define	MST_SLV4_DONE BIT(6)
#define	MST_LOST_ARB BIT(5)
#define	MST_SLV4_NACK BIT(4)
#define	MST_SLV3_NACK BIT(3)
#define	MST_SLV2_NACK BIT(2)
#define	MST_SLV1_NACK BIT(1)
#define	MST_SLV0_NACK BIT(0)
#define	INT_STATUS 0x19 /* WOM_INT PLL_RDY_INT DMP_INT1 I2C_MST_INT */
#define	STS_WOM_INT BIT(3)
#define	STS_PLL_RDY_INT BIT(2)
#define	STS_DMP_INT1 BIT(1)
#define	STS_I2C_MST_INT BIT(0)
#define	INT_STATUS_1 0x1A /* RAW_DATA_0_RDY_INT */
#define	STS_RAW_DATA_0_RDY_INT BIT(0)
#define	INT_STATUS_2 0x1B /* FIFO_OVERFLOW_INT[4:0] */
#define	INT_STATUS_3 0x1C /* FIFO_WM_INT[4:0] */
#define	DELAY_TIMEH 0x28
#define	DELAY_TIMEL 0x29
#define	ACCEL_XOUT_H 0x2D
#define	ACCEL_XOUT_L 0x2E
#define	ACCEL_YOUT_H 0x2F
#define	ACCEL_YOUT_L 0x30
#define	ACCEL_ZOUT_H 0x31
#define	ACCEL_ZOUT_L 0x32
#define	GYRO_XOUT_H 0x33
#define	GYRO_XOUT_L 0x34
#define	GYRO_YOUT_H 0x35
#define	GYRO_YOUT_L 0x36
#define	GYRO_ZOUT_H 0x37
#define	GYRO_ZOUT_L 0x38
#define	TEMP_OUT_H 0x39
#define	TEMP_OUT_L 0x3A
#define	EXT_SLV_SENS_DATA_00 0x3B
#define	EXT_SLV_SENS_DATA_23 0x52 /* contiguous range 0x3B..0x52 */
#define	FIFO_EN_1 0x66 /* SLV3..SLV0 FIFO_EN */
#define	FIFO_EN_2 0x67 /* ACCEL GYRO_Z/Y/X TEMP FIFO_EN */
#define	FIFO_RST 0x68 /* FIFO_RESET[4:0] */
#define	FIFO_MODE 0x69 /* FIFO_MODE[4:0] */
#define	FIFO_COUNTH 0x70
#define	FIFO_COUNTL 0x71
#define	FIFO_R_W 0x72
#define	FIFO_CFG 0x76
#define	REG_BANK_SEL 0x7F /* USER_BANK[1:0] */
#define	SELF_TEST_X_GYRO 0x02 /* XG_ST_DATA[7:0] */
#define	SELF_TEST_Y_GYRO 0x03 /* YG_ST_DATA[7:0] */
#define	SELF_TEST_Z_GYRO 0x04 /* ZG_ST_DATA[7:0] */
#define	SELF_TEST_X_ACCEL 0x0E /* XA_ST_DATA[7:0] */
#define	SELF_TEST_Y_ACCEL 0x0F /* YA_ST_DATA[7:0] */
#define	SELF_TEST_Z_ACCEL 0x10 /* ZA_ST_DATA[7:0] */
#define	XA_OFFS_H 0x14 /* XA_OFFS[14:7] */
#define	XA_OFFS_L 0x15 /* XA_OFFS[6:0] */
#define	YA_OFFS_H 0x17 /* YA_OFFS[14:7] */
#define	YA_OFFS_L 0x18 /* YA_OFFS[6:0] */
#define	ZA_OFFS_H 0x1A /* ZA_OFFS[14:7] */
#define	ZA_OFFS_L 0x1B /* ZA_OFFS[6:0] */
#define	TIMEBASE_CORRECTION_PLL 0x28 /* TBC_PLL[7:0] */
#define	BANK1_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
#define	GYRO_SMPLRT_DIV 0x00 /* GYRO_SMPLRT_DIV[7:0] */
#define	GYRO_CONFIG_1 0x01 /* GYRO_DLPFCFG[2:0] GYRO_FS_SEL[1:0] GYRO_FCHOICE */
#define	GYRO_FCHOICE BIT(0) /* when 0: DLPF on, when 1: off (per datasheet) */
#define	GYRO_FS_SEL_SHIFT 1
#define	GYRO_FS_SEL_MASK (0x3u << GYRO_FS_SEL_SHIFT)
#define	GYRO_FS_250DPS (0u << GYRO_FS_SEL_SHIFT)
#define	GYRO_FS_500DPS (1u << GYRO_FS_SEL_SHIFT)
#define	GYRO_FS_1000DPS (2u << GYRO_FS_SEL_SHIFT)
#define	GYRO_FS_2000DPS (3u << GYRO_FS_SEL_SHIFT)
#define	GYRO_DLPFCFG_SHIFT 5
#define	GYRO_DLPFCFG_MASK (0x7u << GYRO_DLPFCFG_SHIFT)
#define	GYRO_CONFIG_2 0x02 /* XGYRO_CTEN YGYRO_CTEN ZGYRO_CTEN GYRO_AVGCFG[2:0] */
#define	XGYRO_CTEN BIT(5)
#define	YGYRO_CTEN BIT(4)
#define	ZGYRO_CTEN BIT(3)
#define	GYRO_AVGCFG_SHIFT 0
#define	GYRO_AVGCFG_MASK (0x7u << GYRO_AVGCFG_SHIFT)
#define	XG_OFFS_USRH 0x03
#define	XG_OFFS_USRL 0x04
#define	YG_OFFS_USRH 0x05
#define	YG_OFFS_USRL 0x06
#define	ZG_OFFS_USRH 0x07
#define	ZG_OFFS_USRL 0x08
#define	ODR_ALIGN_EN 0x09 /* ODR_ALIGN_EN */
#define	ODR_ALIGN_EN_BIT BIT(0)
#define	ACCEL_SMPLRT_DIV_1 0x10 /* ACCEL_SMPLRT_DIV[11:8] */
#define	ACCEL_SMPLRT_DIV_2 0x11 /* ACCEL_SMPLRT_DIV[7:0] */
#define	ACCEL_INTEL_CTRL 0x12 /* ACCEL_INTEL_EN ACCEL_INTEL_MODE_INT */
#define	ACCEL_INTEL_EN BIT(7)
#define	ACCEL_INTEL_MODE_INT BIT(6)
#define	ACCEL_WOM_THR 0x13 /* WOM_THRESHOLD[7:0] */
#define	ACCEL_CONFIG 0x14 /* ACCEL_DLPFCFG[2:0] ACCEL_FS_SEL[1:0] ACCEL_FCHOICE */
#define	ACCEL_FCHOICE BIT(0)
#define	ACCEL_FS_SEL_SHIFT 1
#define	ACCEL_FS_SEL_MASK (0x3u << ACCEL_FS_SEL_SHIFT)
#define	ACCEL_FS_2G (0u << ACCEL_FS_SEL_SHIFT)
#define	ACCEL_FS_4G (1u << ACCEL_FS_SEL_SHIFT)
#define	ACCEL_FS_8G (2u << ACCEL_FS_SEL_SHIFT)
#define	ACCEL_FS_16G (3u << ACCEL_FS_SEL_SHIFT)
#define	ACCEL_DLPFCFG_SHIFT 5
#define	ACCEL_DLPFCFG_MASK (0x7u << ACCEL_DLPFCFG_SHIFT)
#define	ACCEL_CONFIG_2 0x15 /* AX_ST_EN_REG AY_ST_EN_REG AZ_ST_EN_REG DEC3_CFG[1:0] */
#define	AX_ST_EN_REG BIT(7)
#define	AY_ST_EN_REG BIT(6)
#define	AZ_ST_EN_REG BIT(5)
#define	DEC3_CFG_SHIFT 0
#define	DEC3_CFG_MASK (0x3u << DEC3_CFG_SHIFT)
#define	FSYNC_CONFIG 0x52 /* DELAY_TIME_EN WOF_DEGLITCH_EN WOF_EDGE_INT EXT_SYNC_SET[3:0] */
#define	DELAY_TIME_EN BIT(7)
#define	WOF_DEGLITCH_EN BIT(6)
#define	WOF_EDGE_INT BIT(5)
#define	EXT_SYNC_SET_MASK 0x0F
#define	TEMP_CONFIG 0x53 /* TEMP_DLPFCFG[2:0] */
#define	TEMP_DLPFCFG_SHIFT 5
#define	TEMP_DLPFCFG_MASK (0x7u << TEMP_DLPFCFG_SHIFT)
#define	MOD_CTRL_USR 0x54 /* REG_LP_DMP_EN */
#define	REG_LP_DMP_EN BIT(7)
#define	BANK2_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
#define	I2C_MST_ODR_CONFIG 0x00 /* I2C_MST_ODR_CONFIG[3:0] */
#define	MST_ODR_CFG_MASK 0x0F
#define	I2C_MST_CTRL 0x01 /* MULT_MST_EN - I2C_MST_P_NSR I2C_MST_CLK[3:0] */
#define	MULT_MST_EN BIT(7)
#define	I2C_MST_P_NSR BIT(4)
#define	I2C_MST_CLK_MASK 0x0F
#define	I2C_MST_DELAY_CTRL 0x02 /* DELAY_ES_SHADOW + I2C_SLVx_DELAY_EN bits */
#define	DELAY_ES_SHADOW BIT(7)
#define	I2C_SLV4_DELAY_EN BIT(4)
#define	I2C_SLV3_DELAY_EN BIT(3)
#define	I2C_SLV2_DELAY_EN BIT(2)
#define	I2C_SLV1_DELAY_EN BIT(1)
#define	I2C_SLV0_DELAY_EN BIT(0)
#define	I2C_SLV0_ADDR 0x03 /* RNW + ID[6:0] */
#define	I2C_SLVx_RNW BIT(7)
#define	I2C_SLV0_REG 0x04
#define	I2C_SLV0_CTRL 0x05 /* EN BYTE_SW REG_DIS GRP LENG[3:0] */
#define	I2C_SLVx_EN BIT(7)
#define	I2C_SLVx_BYTE_SW BIT(6)
#define	I2C_SLVx_REG_DIS BIT(5)
#define	I2C_SLVx_GRP BIT(4)
#define	I2C_SLVx_LENG_MASK 0x0F
#define	I2C_SLV0_DO 0x06
#define	I2C_SLV1_ADDR 0x07
#define	I2C_SLV1_REG 0x08
#define	I2C_SLV1_CTRL 0x09
#define	I2C_SLV1_DO 0x0A
#define	I2C_SLV2_ADDR 0x0B
#define	I2C_SLV2_REG 0x0C
#define	I2C_SLV2_CTRL 0x0D
#define	I2C_SLV2_DO 0x0E
#define	I2C_SLV3_ADDR 0x0F
#define	I2C_SLV3_REG 0x10
#define	I2C_SLV3_CTRL 0x11
#define	I2C_SLV3_DO 0x12
#define	I2C_SLV4_ADDR 0x13
#define	I2C_SLV4_REG 0x14
#define	I2C_SLV4_CTRL 0x15 /* EN BYTE_SW REG_DIS DLY[4:0] */
#define	I2C_SLV4_DLY_MASK 0x1F
#define	I2C_SLV4_DO 0x16
#define	I2C_SLV4_DI 0x17
#define	BANK3_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
#define	REG_BANK_SEL_USER_BANK_SHIFT 4
#define	REG_BANK_SEL_USER_BANK_MASK (0x3u << REG_BANK_SEL_USER_BANK_SHIFT)
#define	USER_BANK_0 BANK0
#define	USER_BANK_1 BANK1
#define	USER_BANK_2 BANK2
#define	USER_BANK_3 BANK3
#define	AK09916_I2C_ADDR 0x0C
#define	AK_WIA2 0x01
#define	AK_ST1 0x10
#define	AK_HXL 0x11
#define	AK_ST2 0x18
#define	AK_CNTL2 0x31
#define	AK_CNTL3 0x32
#define	AK_WIA2_VAL 0x09 /* AK09916C WIA2 expected */
#define	INTERNAL_20MHZ 0x00 /* 0: Internal 20 MHz RC */
#define	AUTO_SEL 0x01 /* 1–5: Auto/PLL preferred (use 1 as default) */
#define	CLK_STOP 0x07 /* 7: Stop clock / timing gen reset */
#define	g2 0
#define	g4 1
#define	g8 2
#define	g16 3
#define	ACCEL_FCHOICE_BYPASS 0
#define	ACCEL_FCHOICE_DLPF 1
#define	ACCEL_DLPFCFG_0 0
#define	ACCEL_DLPFCFG_1 1
#define	ACCEL_DLPFCFG_2 2
#define	ACCEL_DLPFCFG_3 3
#define	ACCEL_DLPFCFG_4 4
#define	ACCEL_DLPFCFG_5 5
#define	ACCEL_DLPFCFG_6 6
#define	ACCEL_DLPFCFG_7 7
#define	ACCEL_DEC3_AVG_4 0u /* averages 1 or 4 (depends on FCHOICE) */
#define	ACCEL_DEC3_AVG_8 1u
#define	ACCEL_DEC3_AVG_16 2u
#define	ACCEL_DEC3_AVG_32 3u
#define	ACCEL_SMPLRT_DIV_MIN 0u
#define	ACCEL_SMPLRT_DIV_MAX 4095u
#define	ACCEL_DLPF_BASE_HZ 1125.0f
#define	ACCEL_DLPF_ODR_HZ(div)
#define	ACCEL_BYPASS_3DB_BW_HZ 1209.0f
#define	ACCEL_BYPASS_NBW_HZ 1248.0f
#define	ACCEL_BYPASS_RATE_HZ 4500.0f
#define	ACCEL_DLPF0_3DB_BW_HZ 246.0f
#define	ACCEL_DLPF0_NBW_HZ 265.0f
#define	ACCEL_DLPF1_3DB_BW_HZ 246.0f
#define	ACCEL_DLPF1_NBW_HZ 265.0f
#define	ACCEL_DLPF2_3DB_BW_HZ 111.4f
#define	ACCEL_DLPF2_NBW_HZ 136.0f
#define	ACCEL_DLPF3_3DB_BW_HZ 50.4f
#define	ACCEL_DLPF3_NBW_HZ 68.8f
#define	ACCEL_DLPF4_3DB_BW_HZ 23.9f
#define	ACCEL_DLPF4_NBW_HZ 34.4f
#define	ACCEL_DLPF5_3DB_BW_HZ 11.5f
#define	ACCEL_DLPF5_NBW_HZ 17.0f
#define	ACCEL_DLPF6_3DB_BW_HZ 5.7f
#define	ACCEL_DLPF6_NBW_HZ 8.3f
#define	ACCEL_DLPF7_3DB_BW_HZ 473.0f
#define	ACCEL_DLPF7_NBW_HZ 499.0f
#define	dps250 0
#define	dps500 1
#define	dps1000 2
#define	dps2000 3
#define	GYRO_FCHOICE_BYPASS 0
#define	GYRO_FCHOICE_DLPF 1
#define	GYRO_DLPFCFG_0 0
#define	GYRO_DLPFCFG_1 1
#define	GYRO_DLPFCFG_2 2
#define	GYRO_DLPFCFG_3 3
#define	GYRO_DLPFCFG_4 4
#define	GYRO_DLPFCFG_5 5
#define	GYRO_DLPFCFG_6 6
#define	GYRO_DLPFCFG_7 7
#define	GYRO_SMPLRT_MIN_HZ 4.3f
#define	GYRO_DLPF_BASE_HZ 1100.0f
#define	GYRO_DLPF_ODR_HZ(rate_request)
#define	GYRO_BW_ULTRA_WIDE 0 /* bypass path */
#define	GYRO_BW_WIDE 1 /* e.g., CFG 0/1 */
#define	GYRO_BW_MEDIUM 2 /* e.g., CFG 2/3 */
#define	GYRO_BW_NARROW 3 /* e.g., CFG 4/5/6/7 */
#define	Hz2 0
#define	Hz6 1
#define	Hz8 2
#define	Hz10 3
#define	Hz15 4
#define	Hz20 5
#define	Hz25 6
#define	Hz30 7
#define	LowPower 0
#define	Regular 1
#define	EnhancedRegular 2
#define	HighAccuracy 3

Macro Definition Documentation

◆ ACCEL_BYPASS_3DB_BW_HZ

#define ACCEL_BYPASS_3DB_BW_HZ 1209.0f

Definition at line 369 of file ICM20948_regs.h.

◆ ACCEL_BYPASS_NBW_HZ

#define ACCEL_BYPASS_NBW_HZ 1248.0f

Definition at line 370 of file ICM20948_regs.h.

◆ ACCEL_BYPASS_RATE_HZ

#define ACCEL_BYPASS_RATE_HZ 4500.0f

Definition at line 371 of file ICM20948_regs.h.

◆ ACCEL_CONFIG

#define ACCEL_CONFIG 0x14 /* ACCEL_DLPFCFG[2:0] ACCEL_FS_SEL[1:0] ACCEL_FCHOICE */

Definition at line 209 of file ICM20948_regs.h.

◆ ACCEL_CONFIG_2

#define ACCEL_CONFIG_2 0x15 /* AX_ST_EN_REG AY_ST_EN_REG AZ_ST_EN_REG DEC3_CFG[1:0] */

Definition at line 220 of file ICM20948_regs.h.

◆ ACCEL_DEC3_AVG_16

#define ACCEL_DEC3_AVG_16 2u

Definition at line 356 of file ICM20948_regs.h.

◆ ACCEL_DEC3_AVG_32

#define ACCEL_DEC3_AVG_32 3u

Definition at line 357 of file ICM20948_regs.h.

◆ ACCEL_DEC3_AVG_4

#define ACCEL_DEC3_AVG_4 0u /* averages 1 or 4 (depends on FCHOICE) */

Definition at line 354 of file ICM20948_regs.h.

◆ ACCEL_DEC3_AVG_8

#define ACCEL_DEC3_AVG_8 1u

Definition at line 355 of file ICM20948_regs.h.

◆ ACCEL_DLPF0_3DB_BW_HZ

#define ACCEL_DLPF0_3DB_BW_HZ 246.0f

Definition at line 376 of file ICM20948_regs.h.

◆ ACCEL_DLPF0_NBW_HZ

#define ACCEL_DLPF0_NBW_HZ 265.0f

Definition at line 377 of file ICM20948_regs.h.

◆ ACCEL_DLPF1_3DB_BW_HZ

#define ACCEL_DLPF1_3DB_BW_HZ 246.0f

Definition at line 378 of file ICM20948_regs.h.

◆ ACCEL_DLPF1_NBW_HZ

#define ACCEL_DLPF1_NBW_HZ 265.0f

Definition at line 379 of file ICM20948_regs.h.

◆ ACCEL_DLPF2_3DB_BW_HZ

#define ACCEL_DLPF2_3DB_BW_HZ 111.4f

Definition at line 380 of file ICM20948_regs.h.

◆ ACCEL_DLPF2_NBW_HZ

#define ACCEL_DLPF2_NBW_HZ 136.0f

Definition at line 381 of file ICM20948_regs.h.

◆ ACCEL_DLPF3_3DB_BW_HZ

#define ACCEL_DLPF3_3DB_BW_HZ 50.4f

Definition at line 382 of file ICM20948_regs.h.

◆ ACCEL_DLPF3_NBW_HZ

#define ACCEL_DLPF3_NBW_HZ 68.8f

Definition at line 383 of file ICM20948_regs.h.

◆ ACCEL_DLPF4_3DB_BW_HZ

#define ACCEL_DLPF4_3DB_BW_HZ 23.9f

Definition at line 384 of file ICM20948_regs.h.

◆ ACCEL_DLPF4_NBW_HZ

#define ACCEL_DLPF4_NBW_HZ 34.4f

Definition at line 385 of file ICM20948_regs.h.

◆ ACCEL_DLPF5_3DB_BW_HZ

#define ACCEL_DLPF5_3DB_BW_HZ 11.5f

Definition at line 386 of file ICM20948_regs.h.

◆ ACCEL_DLPF5_NBW_HZ

#define ACCEL_DLPF5_NBW_HZ 17.0f

Definition at line 387 of file ICM20948_regs.h.

◆ ACCEL_DLPF6_3DB_BW_HZ

#define ACCEL_DLPF6_3DB_BW_HZ 5.7f

Definition at line 388 of file ICM20948_regs.h.

◆ ACCEL_DLPF6_NBW_HZ

#define ACCEL_DLPF6_NBW_HZ 8.3f

Definition at line 389 of file ICM20948_regs.h.

◆ ACCEL_DLPF7_3DB_BW_HZ

#define ACCEL_DLPF7_3DB_BW_HZ 473.0f

Definition at line 390 of file ICM20948_regs.h.

◆ ACCEL_DLPF7_NBW_HZ

#define ACCEL_DLPF7_NBW_HZ 499.0f

Definition at line 391 of file ICM20948_regs.h.

◆ ACCEL_DLPF_BASE_HZ

#define ACCEL_DLPF_BASE_HZ 1125.0f

Definition at line 362 of file ICM20948_regs.h.

◆ ACCEL_DLPF_ODR_HZ

#define ACCEL_DLPF_ODR_HZ ( div )

Value:

(ACCEL_DLPF_BASE_HZ / (1.0f + (float)(div)))

ACCEL_DLPF_BASE_HZ

#define ACCEL_DLPF_BASE_HZ

Definition ICM20948_regs.h:362

Definition at line 363 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_0

#define ACCEL_DLPFCFG_0 0

ACCEL_DLPFCFG (0..7) — choose cutoff/noise BW set (when DLPF is ON). Tip: start with ACCEL_DLPFCFG_3 for a good noise/latency tradeoff.

Definition at line 345 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_1

#define ACCEL_DLPFCFG_1 1

Definition at line 346 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_2

#define ACCEL_DLPFCFG_2 2

Definition at line 347 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_3

#define ACCEL_DLPFCFG_3 3

Definition at line 348 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_4

#define ACCEL_DLPFCFG_4 4

Definition at line 349 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_5

#define ACCEL_DLPFCFG_5 5

Definition at line 350 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_6

#define ACCEL_DLPFCFG_6 6

Definition at line 351 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_7

#define ACCEL_DLPFCFG_7 7

Definition at line 352 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_MASK

#define ACCEL_DLPFCFG_MASK (0x7u << ACCEL_DLPFCFG_SHIFT)

Definition at line 218 of file ICM20948_regs.h.

◆ ACCEL_DLPFCFG_SHIFT

#define ACCEL_DLPFCFG_SHIFT 5

Definition at line 217 of file ICM20948_regs.h.

◆ ACCEL_FCHOICE

#define ACCEL_FCHOICE BIT(0)

Definition at line 210 of file ICM20948_regs.h.

◆ ACCEL_FCHOICE_BYPASS

#define ACCEL_FCHOICE_BYPASS 0

Path select for accel:

ACCEL_FCHOICE_BYPASS : DLPF bypassed (very wide BW, fastest)
ACCEL_FCHOICE_DLPF : DLPF enabled (use ACCEL_DLPFCFG + SMPLRT_DIV)

Definition at line 337 of file ICM20948_regs.h.

◆ ACCEL_FCHOICE_DLPF

#define ACCEL_FCHOICE_DLPF 1

Definition at line 338 of file ICM20948_regs.h.

◆ ACCEL_FS_16G

#define ACCEL_FS_16G (3u << ACCEL_FS_SEL_SHIFT)

Definition at line 216 of file ICM20948_regs.h.

◆ ACCEL_FS_2G

#define ACCEL_FS_2G (0u << ACCEL_FS_SEL_SHIFT)

Definition at line 213 of file ICM20948_regs.h.

◆ ACCEL_FS_4G

#define ACCEL_FS_4G (1u << ACCEL_FS_SEL_SHIFT)

Definition at line 214 of file ICM20948_regs.h.

◆ ACCEL_FS_8G

#define ACCEL_FS_8G (2u << ACCEL_FS_SEL_SHIFT)

Definition at line 215 of file ICM20948_regs.h.

◆ ACCEL_FS_SEL_MASK

#define ACCEL_FS_SEL_MASK (0x3u << ACCEL_FS_SEL_SHIFT)

Definition at line 212 of file ICM20948_regs.h.

◆ ACCEL_FS_SEL_SHIFT

#define ACCEL_FS_SEL_SHIFT 1

Definition at line 211 of file ICM20948_regs.h.

◆ ACCEL_INTEL_CTRL

#define ACCEL_INTEL_CTRL 0x12 /* ACCEL_INTEL_EN ACCEL_INTEL_MODE_INT */

Definition at line 203 of file ICM20948_regs.h.

◆ ACCEL_INTEL_EN

#define ACCEL_INTEL_EN BIT(7)

Definition at line 204 of file ICM20948_regs.h.

◆ ACCEL_INTEL_MODE_INT

#define ACCEL_INTEL_MODE_INT BIT(6)

Definition at line 205 of file ICM20948_regs.h.

◆ ACCEL_SMPLRT_DIV_1

#define ACCEL_SMPLRT_DIV_1 0x10 /* ACCEL_SMPLRT_DIV[11:8] */

Definition at line 200 of file ICM20948_regs.h.

◆ ACCEL_SMPLRT_DIV_2

#define ACCEL_SMPLRT_DIV_2 0x11 /* ACCEL_SMPLRT_DIV[7:0] */

Definition at line 201 of file ICM20948_regs.h.

◆ ACCEL_SMPLRT_DIV_MAX

#define ACCEL_SMPLRT_DIV_MAX 4095u

Definition at line 361 of file ICM20948_regs.h.

◆ ACCEL_SMPLRT_DIV_MIN

#define ACCEL_SMPLRT_DIV_MIN 0u

Definition at line 360 of file ICM20948_regs.h.

◆ ACCEL_WOM_THR

#define ACCEL_WOM_THR 0x13 /* WOM_THRESHOLD[7:0] */

Definition at line 207 of file ICM20948_regs.h.

◆ ACCEL_XOUT_H

#define ACCEL_XOUT_H 0x2D

Definition at line 111 of file ICM20948_regs.h.

◆ ACCEL_XOUT_L

#define ACCEL_XOUT_L 0x2E

Definition at line 112 of file ICM20948_regs.h.

◆ ACCEL_YOUT_H

#define ACCEL_YOUT_H 0x2F

Definition at line 113 of file ICM20948_regs.h.

◆ ACCEL_YOUT_L

#define ACCEL_YOUT_L 0x30

Definition at line 114 of file ICM20948_regs.h.

◆ ACCEL_ZOUT_H

#define ACCEL_ZOUT_H 0x31

Definition at line 115 of file ICM20948_regs.h.

◆ ACCEL_ZOUT_L

#define ACCEL_ZOUT_L 0x32

Definition at line 116 of file ICM20948_regs.h.

◆ AK09916_I2C_ADDR

#define AK09916_I2C_ADDR 0x0C

Definition at line 310 of file ICM20948_regs.h.

◆ AK_CNTL2

#define AK_CNTL2 0x31

Definition at line 315 of file ICM20948_regs.h.

◆ AK_CNTL3

#define AK_CNTL3 0x32

Definition at line 316 of file ICM20948_regs.h.

◆ AK_HXL

#define AK_HXL 0x11

Definition at line 313 of file ICM20948_regs.h.

◆ AK_ST1

#define AK_ST1 0x10

Definition at line 312 of file ICM20948_regs.h.

◆ AK_ST2

#define AK_ST2 0x18

Definition at line 314 of file ICM20948_regs.h.

◆ AK_WIA2

#define AK_WIA2 0x01

Definition at line 311 of file ICM20948_regs.h.

◆ AK_WIA2_VAL

#define AK_WIA2_VAL 0x09 /* AK09916C WIA2 expected */

Definition at line 317 of file ICM20948_regs.h.

◆ AUTO_SEL

#define AUTO_SEL 0x01 /* 1–5: Auto/PLL preferred (use 1 as default) */

Definition at line 320 of file ICM20948_regs.h.

◆ AX_ST_EN_REG

#define AX_ST_EN_REG BIT(7)

Definition at line 221 of file ICM20948_regs.h.

◆ AY_ST_EN_REG

#define AY_ST_EN_REG BIT(6)

Definition at line 222 of file ICM20948_regs.h.

◆ AZ_ST_EN_REG

#define AZ_ST_EN_REG BIT(5)

Definition at line 223 of file ICM20948_regs.h.

◆ BANK1_REG_BANK_SEL

#define BANK1_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */

Definition at line 163 of file ICM20948_regs.h.

◆ BANK2_REG_BANK_SEL

#define BANK2_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */

Definition at line 240 of file ICM20948_regs.h.

◆ BANK3_REG_BANK_SEL

#define BANK3_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */

Definition at line 296 of file ICM20948_regs.h.

◆ BYPASS_EN

#define BYPASS_EN BIT(1) /* I2C bypass to aux devices */

Definition at line 71 of file ICM20948_regs.h.

◆ CLK_STOP

#define CLK_STOP 0x07 /* 7: Stop clock / timing gen reset */

Definition at line 321 of file ICM20948_regs.h.

◆ DEC3_CFG_MASK

#define DEC3_CFG_MASK (0x3u << DEC3_CFG_SHIFT)

Definition at line 225 of file ICM20948_regs.h.

◆ DEC3_CFG_SHIFT

#define DEC3_CFG_SHIFT 0

Definition at line 224 of file ICM20948_regs.h.

◆ DELAY_ES_SHADOW

#define DELAY_ES_SHADOW BIT(7)

Definition at line 256 of file ICM20948_regs.h.

◆ DELAY_TIME_EN

#define DELAY_TIME_EN BIT(7)

Definition at line 228 of file ICM20948_regs.h.

◆ DELAY_TIMEH

#define DELAY_TIMEH 0x28

Definition at line 107 of file ICM20948_regs.h.

◆ DELAY_TIMEL

#define DELAY_TIMEL 0x29

Definition at line 108 of file ICM20948_regs.h.

◆ dps1000

#define dps1000 2

Definition at line 398 of file ICM20948_regs.h.

◆ dps2000

#define dps2000 3

Definition at line 399 of file ICM20948_regs.h.

◆ dps250

#define dps250 0

±250/±500/±1000/±2000 dps (maps to FS_SEL 0..3)

Definition at line 396 of file ICM20948_regs.h.

◆ dps500

#define dps500 1

Definition at line 397 of file ICM20948_regs.h.

◆ EnhancedRegular

#define EnhancedRegular 2

Definition at line 456 of file ICM20948_regs.h.

◆ EXT_SLV_SENS_DATA_00

#define EXT_SLV_SENS_DATA_00 0x3B

Definition at line 127 of file ICM20948_regs.h.

◆ EXT_SLV_SENS_DATA_23

#define EXT_SLV_SENS_DATA_23 0x52 /* contiguous range 0x3B..0x52 */

Definition at line 128 of file ICM20948_regs.h.

◆ EXT_SYNC_SET_MASK

#define EXT_SYNC_SET_MASK 0x0F

Definition at line 231 of file ICM20948_regs.h.

◆ FIFO_CFG

#define FIFO_CFG 0x76

Definition at line 138 of file ICM20948_regs.h.

◆ FIFO_COUNTH

#define FIFO_COUNTH 0x70

Definition at line 134 of file ICM20948_regs.h.

◆ FIFO_COUNTL

#define FIFO_COUNTL 0x71

Definition at line 135 of file ICM20948_regs.h.

◆ FIFO_EN_1

#define FIFO_EN_1 0x66 /* SLV3..SLV0 FIFO_EN */

Definition at line 130 of file ICM20948_regs.h.

◆ FIFO_EN_2

#define FIFO_EN_2 0x67 /* ACCEL GYRO_Z/Y/X TEMP FIFO_EN */

Definition at line 131 of file ICM20948_regs.h.

◆ FIFO_MODE

#define FIFO_MODE 0x69 /* FIFO_MODE[4:0] */

Definition at line 133 of file ICM20948_regs.h.

◆ FIFO_R_W

#define FIFO_R_W 0x72

Definition at line 136 of file ICM20948_regs.h.

◆ FIFO_RST

#define FIFO_RST 0x68 /* FIFO_RESET[4:0] */

Definition at line 132 of file ICM20948_regs.h.

◆ FSYNC_CONFIG

#define FSYNC_CONFIG 0x52 /* DELAY_TIME_EN WOF_DEGLITCH_EN WOF_EDGE_INT EXT_SYNC_SET[3:0] */

Definition at line 227 of file ICM20948_regs.h.

◆ FSYNC_INT_MODE_EN

#define FSYNC_INT_MODE_EN BIT(2)

Definition at line 70 of file ICM20948_regs.h.

◆ g16

#define g16 3

Definition at line 329 of file ICM20948_regs.h.

◆ g2

#define g2 0

±2g / ±4g / ±8g / ±16g (maps to FS_SEL 0..3)

Definition at line 326 of file ICM20948_regs.h.

◆ g4

#define g4 1

Definition at line 327 of file ICM20948_regs.h.

◆ g8

#define g8 2

Definition at line 328 of file ICM20948_regs.h.

◆ GYRO_AVGCFG_MASK

#define GYRO_AVGCFG_MASK (0x7u << GYRO_AVGCFG_SHIFT)

Definition at line 188 of file ICM20948_regs.h.

◆ GYRO_AVGCFG_SHIFT

#define GYRO_AVGCFG_SHIFT 0

Definition at line 187 of file ICM20948_regs.h.

◆ GYRO_BW_MEDIUM

#define GYRO_BW_MEDIUM 2 /* e.g., CFG 2/3 */

Definition at line 435 of file ICM20948_regs.h.

◆ GYRO_BW_NARROW

#define GYRO_BW_NARROW 3 /* e.g., CFG 4/5/6/7 */

Definition at line 436 of file ICM20948_regs.h.

◆ GYRO_BW_ULTRA_WIDE

#define GYRO_BW_ULTRA_WIDE 0 /* bypass path */

Definition at line 433 of file ICM20948_regs.h.

◆ GYRO_BW_WIDE

#define GYRO_BW_WIDE 1 /* e.g., CFG 0/1 */

Definition at line 434 of file ICM20948_regs.h.

◆ GYRO_CONFIG_1

#define GYRO_CONFIG_1 0x01 /* GYRO_DLPFCFG[2:0] GYRO_FS_SEL[1:0] GYRO_FCHOICE */

Definition at line 172 of file ICM20948_regs.h.

◆ GYRO_CONFIG_2

#define GYRO_CONFIG_2 0x02 /* XGYRO_CTEN YGYRO_CTEN ZGYRO_CTEN GYRO_AVGCFG[2:0] */

Definition at line 183 of file ICM20948_regs.h.

◆ GYRO_DLPF_BASE_HZ

#define GYRO_DLPF_BASE_HZ 1100.0f

Definition at line 426 of file ICM20948_regs.h.

◆ GYRO_DLPF_ODR_HZ

#define GYRO_DLPF_ODR_HZ ( rate_request )

Value:

(rate_request) /* symbolic; your driver computes DIV = round(1100/rate)-1 */

Definition at line 427 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_0

#define GYRO_DLPFCFG_0 0

GYRO_DLPFCFG (0..7) — choose cutoff/noise BW set (when DLPF is ON). Tip: start with GYRO_DLPFCFG_3 or _2 for balanced noise/latency.

Definition at line 415 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_1

#define GYRO_DLPFCFG_1 1

Definition at line 416 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_2

#define GYRO_DLPFCFG_2 2

Definition at line 417 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_3

#define GYRO_DLPFCFG_3 3

Definition at line 418 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_4

#define GYRO_DLPFCFG_4 4

Definition at line 419 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_5

#define GYRO_DLPFCFG_5 5

Definition at line 420 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_6

#define GYRO_DLPFCFG_6 6

Definition at line 421 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_7

#define GYRO_DLPFCFG_7 7

Definition at line 422 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_MASK

#define GYRO_DLPFCFG_MASK (0x7u << GYRO_DLPFCFG_SHIFT)

Definition at line 181 of file ICM20948_regs.h.

◆ GYRO_DLPFCFG_SHIFT

#define GYRO_DLPFCFG_SHIFT 5

Definition at line 180 of file ICM20948_regs.h.

◆ GYRO_FCHOICE

#define GYRO_FCHOICE BIT(0) /* when 0: DLPF on, when 1: off (per datasheet) */

Definition at line 173 of file ICM20948_regs.h.

◆ GYRO_FCHOICE_BYPASS

#define GYRO_FCHOICE_BYPASS 0

Path select for gyro:

GYRO_FCHOICE_BYPASS : DLPF bypassed (widest BW, fastest)
GYRO_FCHOICE_DLPF : DLPF enabled (use GYRO_DLPFCFG + SMPLRT_DIV)

Definition at line 407 of file ICM20948_regs.h.

◆ GYRO_FCHOICE_DLPF

#define GYRO_FCHOICE_DLPF 1

Definition at line 408 of file ICM20948_regs.h.

◆ GYRO_FS_1000DPS

#define GYRO_FS_1000DPS (2u << GYRO_FS_SEL_SHIFT)

Definition at line 178 of file ICM20948_regs.h.

◆ GYRO_FS_2000DPS

#define GYRO_FS_2000DPS (3u << GYRO_FS_SEL_SHIFT)

Definition at line 179 of file ICM20948_regs.h.

◆ GYRO_FS_250DPS

#define GYRO_FS_250DPS (0u << GYRO_FS_SEL_SHIFT)

Definition at line 176 of file ICM20948_regs.h.

◆ GYRO_FS_500DPS

#define GYRO_FS_500DPS (1u << GYRO_FS_SEL_SHIFT)

Definition at line 177 of file ICM20948_regs.h.

◆ GYRO_FS_SEL_MASK

#define GYRO_FS_SEL_MASK (0x3u << GYRO_FS_SEL_SHIFT)

Definition at line 175 of file ICM20948_regs.h.

◆ GYRO_FS_SEL_SHIFT

#define GYRO_FS_SEL_SHIFT 1

Definition at line 174 of file ICM20948_regs.h.

◆ GYRO_SMPLRT_DIV

#define GYRO_SMPLRT_DIV 0x00 /* GYRO_SMPLRT_DIV[7:0] */

Gyro/Accel configuration, offsets, FSYNC, temperature filter

Definition at line 170 of file ICM20948_regs.h.

◆ GYRO_SMPLRT_MIN_HZ

#define GYRO_SMPLRT_MIN_HZ 4.3f

Definition at line 425 of file ICM20948_regs.h.

◆ GYRO_XOUT_H

#define GYRO_XOUT_H 0x33

Definition at line 117 of file ICM20948_regs.h.

◆ GYRO_XOUT_L

#define GYRO_XOUT_L 0x34

Definition at line 118 of file ICM20948_regs.h.

◆ GYRO_YOUT_H

#define GYRO_YOUT_H 0x35

Definition at line 119 of file ICM20948_regs.h.

◆ GYRO_YOUT_L

#define GYRO_YOUT_L 0x36

Definition at line 120 of file ICM20948_regs.h.

◆ GYRO_ZOUT_H

#define GYRO_ZOUT_H 0x37

Definition at line 121 of file ICM20948_regs.h.

◆ GYRO_ZOUT_L

#define GYRO_ZOUT_L 0x38

Definition at line 122 of file ICM20948_regs.h.

◆ HighAccuracy

#define HighAccuracy 3

Definition at line 457 of file ICM20948_regs.h.

◆ Hz10

#define Hz10 3

Definition at line 443 of file ICM20948_regs.h.

◆ Hz15

#define Hz15 4

Definition at line 444 of file ICM20948_regs.h.

◆ Hz2

#define Hz2 0

Friendly ODR presets you can map to dividers

Definition at line 440 of file ICM20948_regs.h.

◆ Hz20

#define Hz20 5

Definition at line 445 of file ICM20948_regs.h.

◆ Hz25

#define Hz25 6

Definition at line 446 of file ICM20948_regs.h.

◆ Hz30

#define Hz30 7

Definition at line 447 of file ICM20948_regs.h.

◆ Hz6

#define Hz6 1

Definition at line 441 of file ICM20948_regs.h.

◆ Hz8

#define Hz8 2

Definition at line 442 of file ICM20948_regs.h.

◆ I2C_MST_CLK_MASK

#define I2C_MST_CLK_MASK 0x0F

Definition at line 253 of file ICM20948_regs.h.

◆ I2C_MST_CTRL

#define I2C_MST_CTRL 0x01 /* MULT_MST_EN - I2C_MST_P_NSR I2C_MST_CLK[3:0] */

Definition at line 250 of file ICM20948_regs.h.

◆ I2C_MST_DELAY_CTRL

#define I2C_MST_DELAY_CTRL 0x02 /* DELAY_ES_SHADOW + I2C_SLVx_DELAY_EN bits */

Definition at line 255 of file ICM20948_regs.h.

◆ I2C_MST_ODR_CONFIG

#define I2C_MST_ODR_CONFIG 0x00 /* I2C_MST_ODR_CONFIG[3:0] */

I2C master (aux) interface and slave windows

Definition at line 247 of file ICM20948_regs.h.

◆ I2C_MST_P_NSR

#define I2C_MST_P_NSR BIT(4)

Definition at line 252 of file ICM20948_regs.h.

◆ I2C_MST_STATUS

#define I2C_MST_STATUS 0x17 /* PASS_THROUGH, *_DONE, *_NACK, LOST_ARB */

Definition at line 86 of file ICM20948_regs.h.

◆ I2C_SLV0_ADDR

#define I2C_SLV0_ADDR 0x03 /* RNW + ID[6:0] */

Definition at line 263 of file ICM20948_regs.h.

◆ I2C_SLV0_CTRL

#define I2C_SLV0_CTRL 0x05 /* EN BYTE_SW REG_DIS GRP LENG[3:0] */

Definition at line 266 of file ICM20948_regs.h.

◆ I2C_SLV0_DELAY_EN

#define I2C_SLV0_DELAY_EN BIT(0)

Definition at line 261 of file ICM20948_regs.h.

◆ I2C_SLV0_DO

#define I2C_SLV0_DO 0x06

Definition at line 272 of file ICM20948_regs.h.

◆ I2C_SLV0_REG

#define I2C_SLV0_REG 0x04

Definition at line 265 of file ICM20948_regs.h.

◆ I2C_SLV1_ADDR

#define I2C_SLV1_ADDR 0x07

Definition at line 274 of file ICM20948_regs.h.

◆ I2C_SLV1_CTRL

#define I2C_SLV1_CTRL 0x09

Definition at line 276 of file ICM20948_regs.h.

◆ I2C_SLV1_DELAY_EN

#define I2C_SLV1_DELAY_EN BIT(1)

Definition at line 260 of file ICM20948_regs.h.

◆ I2C_SLV1_DO

#define I2C_SLV1_DO 0x0A

Definition at line 277 of file ICM20948_regs.h.

◆ I2C_SLV1_REG

#define I2C_SLV1_REG 0x08

Definition at line 275 of file ICM20948_regs.h.

◆ I2C_SLV2_ADDR

#define I2C_SLV2_ADDR 0x0B

Definition at line 279 of file ICM20948_regs.h.

◆ I2C_SLV2_CTRL

#define I2C_SLV2_CTRL 0x0D

Definition at line 281 of file ICM20948_regs.h.

◆ I2C_SLV2_DELAY_EN

#define I2C_SLV2_DELAY_EN BIT(2)

Definition at line 259 of file ICM20948_regs.h.

◆ I2C_SLV2_DO

#define I2C_SLV2_DO 0x0E

Definition at line 282 of file ICM20948_regs.h.

◆ I2C_SLV2_REG

#define I2C_SLV2_REG 0x0C

Definition at line 280 of file ICM20948_regs.h.

◆ I2C_SLV3_ADDR

#define I2C_SLV3_ADDR 0x0F

Definition at line 284 of file ICM20948_regs.h.

◆ I2C_SLV3_CTRL

#define I2C_SLV3_CTRL 0x11

Definition at line 286 of file ICM20948_regs.h.

◆ I2C_SLV3_DELAY_EN

#define I2C_SLV3_DELAY_EN BIT(3)

Definition at line 258 of file ICM20948_regs.h.

◆ I2C_SLV3_DO

#define I2C_SLV3_DO 0x12

Definition at line 287 of file ICM20948_regs.h.

◆ I2C_SLV3_REG

#define I2C_SLV3_REG 0x10

Definition at line 285 of file ICM20948_regs.h.

◆ I2C_SLV4_ADDR

#define I2C_SLV4_ADDR 0x13

Definition at line 289 of file ICM20948_regs.h.

◆ I2C_SLV4_CTRL

#define I2C_SLV4_CTRL 0x15 /* EN BYTE_SW REG_DIS DLY[4:0] */

Definition at line 291 of file ICM20948_regs.h.

◆ I2C_SLV4_DELAY_EN

#define I2C_SLV4_DELAY_EN BIT(4)

Definition at line 257 of file ICM20948_regs.h.

◆ I2C_SLV4_DI

#define I2C_SLV4_DI 0x17

Definition at line 294 of file ICM20948_regs.h.

◆ I2C_SLV4_DLY_MASK

#define I2C_SLV4_DLY_MASK 0x1F

Definition at line 292 of file ICM20948_regs.h.

◆ I2C_SLV4_DO

#define I2C_SLV4_DO 0x16

Definition at line 293 of file ICM20948_regs.h.

◆ I2C_SLV4_REG

#define I2C_SLV4_REG 0x14

Definition at line 290 of file ICM20948_regs.h.

◆ I2C_SLVx_BYTE_SW

#define I2C_SLVx_BYTE_SW BIT(6)

Definition at line 268 of file ICM20948_regs.h.

◆ I2C_SLVx_EN

#define I2C_SLVx_EN BIT(7)

Definition at line 267 of file ICM20948_regs.h.

◆ I2C_SLVx_GRP

#define I2C_SLVx_GRP BIT(4)

Definition at line 270 of file ICM20948_regs.h.

◆ I2C_SLVx_LENG_MASK

#define I2C_SLVx_LENG_MASK 0x0F

Definition at line 271 of file ICM20948_regs.h.

◆ I2C_SLVx_REG_DIS

#define I2C_SLVx_REG_DIS BIT(5)

Definition at line 269 of file ICM20948_regs.h.

◆ I2C_SLVx_RNW

#define I2C_SLVx_RNW BIT(7)

Definition at line 264 of file ICM20948_regs.h.

◆ INT1_ACTL

#define INT1_ACTL BIT(7) /* active low */

Definition at line 65 of file ICM20948_regs.h.

◆ INT1_LATCH_INT_EN

#define INT1_LATCH_INT_EN BIT(5) /* latch until status read */

Definition at line 67 of file ICM20948_regs.h.

◆ INT1_OPEN

#define INT1_OPEN BIT(6) /* open-drain */

Definition at line 66 of file ICM20948_regs.h.

◆ INT_ACTL_FSYNC

#define INT_ACTL_FSYNC BIT(3)

Definition at line 69 of file ICM20948_regs.h.

◆ INT_ANYRD_2CLEAR

#define INT_ANYRD_2CLEAR BIT(4)

Definition at line 68 of file ICM20948_regs.h.

◆ INT_DMP_INT1_EN

#define INT_DMP_INT1_EN BIT(1)

Definition at line 77 of file ICM20948_regs.h.

◆ INT_ENABLE

#define INT_ENABLE 0x10 /* REG_WOF_EN - WOM_INT_EN PLL_RDY_EN DMP_INT1_EN I2C_MST_INT_EN */

Definition at line 73 of file ICM20948_regs.h.

◆ INT_ENABLE_1

#define INT_ENABLE_1 0x11 /* RAW_DATA_0_RDY_EN */

Definition at line 80 of file ICM20948_regs.h.

◆ INT_ENABLE_2

#define INT_ENABLE_2 0x12 /* FIFO_OVERFLOW_EN[4:0] */

Definition at line 83 of file ICM20948_regs.h.

◆ INT_ENABLE_3

#define INT_ENABLE_3 0x13 /* FIFO_WM_EN[4:0] */

Definition at line 84 of file ICM20948_regs.h.

◆ INT_I2C_MST_INT_EN

#define INT_I2C_MST_INT_EN BIT(0)

Definition at line 78 of file ICM20948_regs.h.

◆ INT_PIN_CFG

#define INT_PIN_CFG 0x0F /* INT1_ACTL INT1_OPEN INT1_LATCH_INT_EN INT_ANYRD_2CLEAR ACTL_FSYNC FSYNC_INT_MODE_EN BYPASS_EN - */

Definition at line 64 of file ICM20948_regs.h.

◆ INT_PLL_RDY_EN

#define INT_PLL_RDY_EN BIT(2)

Definition at line 76 of file ICM20948_regs.h.

◆ INT_RAW_DATA_0_RDY_EN

#define INT_RAW_DATA_0_RDY_EN BIT(0)

Definition at line 81 of file ICM20948_regs.h.

◆ INT_REG_WOF_EN

#define INT_REG_WOF_EN BIT(7)

Definition at line 74 of file ICM20948_regs.h.

◆ INT_STATUS

#define INT_STATUS 0x19 /* WOM_INT PLL_RDY_INT DMP_INT1 I2C_MST_INT */

Definition at line 96 of file ICM20948_regs.h.

◆ INT_STATUS_1

#define INT_STATUS_1 0x1A /* RAW_DATA_0_RDY_INT */

Definition at line 102 of file ICM20948_regs.h.

◆ INT_STATUS_2

#define INT_STATUS_2 0x1B /* FIFO_OVERFLOW_INT[4:0] */

Definition at line 104 of file ICM20948_regs.h.

◆ INT_STATUS_3

#define INT_STATUS_3 0x1C /* FIFO_WM_INT[4:0] */

Definition at line 105 of file ICM20948_regs.h.

◆ INT_WOM_INT_EN

#define INT_WOM_INT_EN BIT(3)

Definition at line 75 of file ICM20948_regs.h.

◆ INTERNAL_20MHZ

#define INTERNAL_20MHZ 0x00 /* 0: Internal 20 MHz RC */

Definition at line 319 of file ICM20948_regs.h.

◆ LowPower

#define LowPower 0

Generic power or fusion quality modes (BNO-style). Map to sensor-specific sequences inside your driver.

Definition at line 454 of file ICM20948_regs.h.

◆ LP_ACCEL_CYCLE

#define LP_ACCEL_CYCLE BIT(5)

Definition at line 47 of file ICM20948_regs.h.

◆ LP_CONFIG

#define LP_CONFIG 0x05 /* I2C_MST_CYCLE ACCEL_CYCLE GYRO_CYCLE - */

Definition at line 45 of file ICM20948_regs.h.

◆ LP_GYRO_CYCLE

#define LP_GYRO_CYCLE BIT(4)

Definition at line 48 of file ICM20948_regs.h.

◆ LP_I2C_MST_CYCLE

#define LP_I2C_MST_CYCLE BIT(6)

Definition at line 46 of file ICM20948_regs.h.

◆ MOD_CTRL_USR

#define MOD_CTRL_USR 0x54 /* REG_LP_DMP_EN */

Definition at line 237 of file ICM20948_regs.h.

◆ MST_LOST_ARB

#define MST_LOST_ARB BIT(5)

Definition at line 89 of file ICM20948_regs.h.

◆ MST_ODR_CFG_MASK

#define MST_ODR_CFG_MASK 0x0F

Definition at line 248 of file ICM20948_regs.h.

◆ MST_PASS_THROUGH

#define MST_PASS_THROUGH BIT(7)

Definition at line 87 of file ICM20948_regs.h.

◆ MST_SLV0_NACK

#define MST_SLV0_NACK BIT(0)

Definition at line 94 of file ICM20948_regs.h.

◆ MST_SLV1_NACK

#define MST_SLV1_NACK BIT(1)

Definition at line 93 of file ICM20948_regs.h.

◆ MST_SLV2_NACK

#define MST_SLV2_NACK BIT(2)

Definition at line 92 of file ICM20948_regs.h.

◆ MST_SLV3_NACK

#define MST_SLV3_NACK BIT(3)

Definition at line 91 of file ICM20948_regs.h.

◆ MST_SLV4_DONE

#define MST_SLV4_DONE BIT(6)

Definition at line 88 of file ICM20948_regs.h.

◆ MST_SLV4_NACK

#define MST_SLV4_NACK BIT(4)

Definition at line 90 of file ICM20948_regs.h.

◆ MULT_MST_EN

#define MULT_MST_EN BIT(7)

Definition at line 251 of file ICM20948_regs.h.

◆ ODR_ALIGN_EN

#define ODR_ALIGN_EN 0x09 /* ODR_ALIGN_EN */

Definition at line 197 of file ICM20948_regs.h.

◆ ODR_ALIGN_EN_BIT

#define ODR_ALIGN_EN_BIT BIT(0)

Definition at line 198 of file ICM20948_regs.h.

◆ PWR_CLKSEL_AUTO

#define PWR_CLKSEL_AUTO 0x01 /* typical: auto selects best source */

Definition at line 57 of file ICM20948_regs.h.

◆ PWR_CLKSEL_INT_20MHZ

#define PWR_CLKSEL_INT_20MHZ 0x01

Definition at line 56 of file ICM20948_regs.h.

◆ PWR_CLKSEL_MASK

#define PWR_CLKSEL_MASK 0x07

Definition at line 55 of file ICM20948_regs.h.

◆ PWR_DEVICE_RESET

#define PWR_DEVICE_RESET BIT(7)

Definition at line 51 of file ICM20948_regs.h.

◆ PWR_DISABLE_ACCEL

#define PWR_DISABLE_ACCEL BIT(3)

Definition at line 60 of file ICM20948_regs.h.

◆ PWR_DISABLE_GYRO

#define PWR_DISABLE_GYRO BIT(0)

Definition at line 61 of file ICM20948_regs.h.

◆ PWR_LP_EN

#define PWR_LP_EN BIT(5)

Definition at line 53 of file ICM20948_regs.h.

◆ PWR_MGMT_1

#define PWR_MGMT_1 0x06 /* DEVICE_RESET SLEEP LP_EN - TEMP_DIS CLKSEL[2:0] */

Definition at line 50 of file ICM20948_regs.h.

◆ PWR_MGMT_2

#define PWR_MGMT_2 0x07 /* - DISABLE_ACCEL DISABLE_GYRO */

Definition at line 59 of file ICM20948_regs.h.

◆ PWR_SLEEP

#define PWR_SLEEP BIT(6)

Definition at line 52 of file ICM20948_regs.h.

◆ PWR_TEMP_DIS

#define PWR_TEMP_DIS BIT(3)

Definition at line 54 of file ICM20948_regs.h.

◆ REG_BANK_SEL

#define REG_BANK_SEL 0x7F /* USER_BANK[1:0] */

Definition at line 140 of file ICM20948_regs.h.

◆ REG_BANK_SEL_USER_BANK_MASK

#define REG_BANK_SEL_USER_BANK_MASK (0x3u << REG_BANK_SEL_USER_BANK_SHIFT)

Definition at line 303 of file ICM20948_regs.h.

◆ REG_BANK_SEL_USER_BANK_SHIFT

#define REG_BANK_SEL_USER_BANK_SHIFT 4

Definition at line 302 of file ICM20948_regs.h.

◆ REG_LP_DMP_EN

#define REG_LP_DMP_EN BIT(7)

Definition at line 238 of file ICM20948_regs.h.

◆ Regular

#define Regular 1

Definition at line 455 of file ICM20948_regs.h.

◆ SELF_TEST_X_ACCEL

#define SELF_TEST_X_ACCEL 0x0E /* XA_ST_DATA[7:0] */

Definition at line 150 of file ICM20948_regs.h.

◆ SELF_TEST_X_GYRO

#define SELF_TEST_X_GYRO 0x02 /* XG_ST_DATA[7:0] */

Self-test / accel offsets / timebase

Definition at line 147 of file ICM20948_regs.h.

◆ SELF_TEST_Y_ACCEL

#define SELF_TEST_Y_ACCEL 0x0F /* YA_ST_DATA[7:0] */

Definition at line 151 of file ICM20948_regs.h.

◆ SELF_TEST_Y_GYRO

#define SELF_TEST_Y_GYRO 0x03 /* YG_ST_DATA[7:0] */

Definition at line 148 of file ICM20948_regs.h.

◆ SELF_TEST_Z_ACCEL

#define SELF_TEST_Z_ACCEL 0x10 /* ZA_ST_DATA[7:0] */

Definition at line 152 of file ICM20948_regs.h.

◆ SELF_TEST_Z_GYRO

#define SELF_TEST_Z_GYRO 0x04 /* ZG_ST_DATA[7:0] */

Definition at line 149 of file ICM20948_regs.h.

◆ STS_DMP_INT1

#define STS_DMP_INT1 BIT(1)

Definition at line 99 of file ICM20948_regs.h.

◆ STS_I2C_MST_INT

#define STS_I2C_MST_INT BIT(0)

Definition at line 100 of file ICM20948_regs.h.

◆ STS_PLL_RDY_INT

#define STS_PLL_RDY_INT BIT(2)

Definition at line 98 of file ICM20948_regs.h.

◆ STS_RAW_DATA_0_RDY_INT

#define STS_RAW_DATA_0_RDY_INT BIT(0)

Definition at line 103 of file ICM20948_regs.h.

◆ STS_WOM_INT

#define STS_WOM_INT BIT(3)

Definition at line 97 of file ICM20948_regs.h.

◆ TEMP_CONFIG

#define TEMP_CONFIG 0x53 /* TEMP_DLPFCFG[2:0] */

Definition at line 233 of file ICM20948_regs.h.

◆ TEMP_DLPFCFG_MASK

#define TEMP_DLPFCFG_MASK (0x7u << TEMP_DLPFCFG_SHIFT)

Definition at line 235 of file ICM20948_regs.h.

◆ TEMP_DLPFCFG_SHIFT

#define TEMP_DLPFCFG_SHIFT 5

Definition at line 234 of file ICM20948_regs.h.

◆ TEMP_OUT_H

#define TEMP_OUT_H 0x39

Definition at line 123 of file ICM20948_regs.h.

◆ TEMP_OUT_L

#define TEMP_OUT_L 0x3A

Definition at line 124 of file ICM20948_regs.h.

◆ TIMEBASE_CORRECTION_PLL

#define TIMEBASE_CORRECTION_PLL 0x28 /* TBC_PLL[7:0] */

Definition at line 161 of file ICM20948_regs.h.

◆ USER_BANK_0

#define USER_BANK_0 BANK0

Definition at line 304 of file ICM20948_regs.h.

◆ USER_BANK_1

#define USER_BANK_1 BANK1

Definition at line 305 of file ICM20948_regs.h.

◆ USER_BANK_2

#define USER_BANK_2 BANK2

Definition at line 306 of file ICM20948_regs.h.

◆ USER_BANK_3

#define USER_BANK_3 BANK3

Definition at line 307 of file ICM20948_regs.h.

◆ USER_CTRL

#define USER_CTRL 0x03 /* DMP_EN FIFO_EN I2C_MST_EN I2C_IF_DIS DMP_RST SRAM_RST I2C_MST_RST - */

Definition at line 35 of file ICM20948_regs.h.

◆ USER_CTRL_DMP_EN

#define USER_CTRL_DMP_EN BIT(7)

Definition at line 37 of file ICM20948_regs.h.

◆ USER_CTRL_DMP_RST

#define USER_CTRL_DMP_RST BIT(3)

Definition at line 41 of file ICM20948_regs.h.

◆ USER_CTRL_FIFO_EN

#define USER_CTRL_FIFO_EN BIT(6)

Definition at line 38 of file ICM20948_regs.h.

◆ USER_CTRL_I2C_IF_DIS

#define USER_CTRL_I2C_IF_DIS BIT(4)

Definition at line 40 of file ICM20948_regs.h.

◆ USER_CTRL_I2C_MST_EN

#define USER_CTRL_I2C_MST_EN BIT(5)

Definition at line 39 of file ICM20948_regs.h.

◆ USER_CTRL_I2C_MST_RST

#define USER_CTRL_I2C_MST_RST BIT(1)

Definition at line 43 of file ICM20948_regs.h.

◆ USER_CTRL_SRAM_RST

#define USER_CTRL_SRAM_RST BIT(2)

Definition at line 42 of file ICM20948_regs.h.

◆ WHO_AM_I

#define WHO_AM_I 0x00 /* WHO_AM_I[7:0] */

7Semi comment style

Full ICM-20948 register map (Banks 0–3) + key bit fields
Simple, portable #defines for firmware use
Datasheet naming kept where practical; fields grouped by bank

Notes

WHO_AM_I expected value: 0xEA
Select register bank via REG_BANK_SEL in any bank
Use BANK(n) helper or write raw values 0x00/0x10/0x20/0x30
Identity / power / interrupts / sensor data

Definition at line 32 of file ICM20948_regs.h.

◆ WHO_AM_I_VAL

#define WHO_AM_I_VAL 0xEA

Definition at line 33 of file ICM20948_regs.h.

◆ WOF_DEGLITCH_EN

#define WOF_DEGLITCH_EN BIT(6)

Definition at line 229 of file ICM20948_regs.h.

◆ WOF_EDGE_INT

#define WOF_EDGE_INT BIT(5)

Definition at line 230 of file ICM20948_regs.h.

◆ XA_OFFS_H

#define XA_OFFS_H 0x14 /* XA_OFFS[14:7] */

Definition at line 154 of file ICM20948_regs.h.

◆ XA_OFFS_L

#define XA_OFFS_L 0x15 /* XA_OFFS[6:0] */

Definition at line 155 of file ICM20948_regs.h.

◆ XG_OFFS_USRH

#define XG_OFFS_USRH 0x03

Definition at line 190 of file ICM20948_regs.h.

◆ XG_OFFS_USRL

#define XG_OFFS_USRL 0x04

Definition at line 191 of file ICM20948_regs.h.

◆ XGYRO_CTEN

#define XGYRO_CTEN BIT(5)

Definition at line 184 of file ICM20948_regs.h.

◆ YA_OFFS_H

#define YA_OFFS_H 0x17 /* YA_OFFS[14:7] */

Definition at line 156 of file ICM20948_regs.h.

◆ YA_OFFS_L

#define YA_OFFS_L 0x18 /* YA_OFFS[6:0] */

Definition at line 157 of file ICM20948_regs.h.

◆ YG_OFFS_USRH

#define YG_OFFS_USRH 0x05

Definition at line 192 of file ICM20948_regs.h.

◆ YG_OFFS_USRL

#define YG_OFFS_USRL 0x06

Definition at line 193 of file ICM20948_regs.h.

◆ YGYRO_CTEN

#define YGYRO_CTEN BIT(4)

Definition at line 185 of file ICM20948_regs.h.

◆ ZA_OFFS_H

#define ZA_OFFS_H 0x1A /* ZA_OFFS[14:7] */

Definition at line 158 of file ICM20948_regs.h.

◆ ZA_OFFS_L

#define ZA_OFFS_L 0x1B /* ZA_OFFS[6:0] */

Definition at line 159 of file ICM20948_regs.h.

◆ ZG_OFFS_USRH

#define ZG_OFFS_USRH 0x07

Definition at line 194 of file ICM20948_regs.h.

◆ ZG_OFFS_USRL

#define ZG_OFFS_USRL 0x08

Definition at line 195 of file ICM20948_regs.h.

◆ ZGYRO_CTEN

#define ZGYRO_CTEN BIT(3)

Definition at line 186 of file ICM20948_regs.h.

Macros