DevLab_ICM20948 1.0.0 Driver para sensor ICM-20948

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ICM20948_regs.h
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1#ifndef ICM20948_REGS_H
2#define ICM20948_REGS_H
3
4/**
5 * 7Semi comment style
6 * - Full ICM-20948 register map (Banks 0–3) + key bit fields
7 * - Simple, portable #defines for firmware use
8 * - Datasheet naming kept where practical; fields grouped by bank
9 *
10 * Notes
11 * - WHO_AM_I expected value: 0xEA
12 * - Select register bank via REG_BANK_SEL in any bank
13 * - Use BANK(n) helper or write raw values 0x00/0x10/0x20/0x30
14 */
15
16/* -------- Common helpers -------- */
17#ifndef BIT
18#define BIT(n) (1u << (n))
19#endif
20
21// #define BANK(n) ((uint8_t)((n) << 4))
22// #define BANK0 BANK(0)
23// #define BANK1 BANK(1)
24// #define BANK2 BANK(2)
25// #define BANK3 BANK(3)
26
27/* ========================================================================== */
28/* BANK 0 */
29/* ========================================================================== */
30
31/** - Identity / power / interrupts / sensor data */
32#define WHO_AM_I 0x00 /* WHO_AM_I[7:0] */
33#define WHO_AM_I_VAL 0xEA
34
35#define USER_CTRL 0x03 /* DMP_EN FIFO_EN I2C_MST_EN I2C_IF_DIS DMP_RST SRAM_RST I2C_MST_RST - */
36/* bits */
37#define USER_CTRL_DMP_EN BIT(7)
38#define USER_CTRL_FIFO_EN BIT(6)
39#define USER_CTRL_I2C_MST_EN BIT(5)
40#define USER_CTRL_I2C_IF_DIS BIT(4)
41#define USER_CTRL_DMP_RST BIT(3)
42#define USER_CTRL_SRAM_RST BIT(2)
43#define USER_CTRL_I2C_MST_RST BIT(1)
44
45#define LP_CONFIG 0x05 /* I2C_MST_CYCLE ACCEL_CYCLE GYRO_CYCLE - */
46#define LP_I2C_MST_CYCLE BIT(6)
47#define LP_ACCEL_CYCLE BIT(5)
48#define LP_GYRO_CYCLE BIT(4)
49
50#define PWR_MGMT_1 0x06 /* DEVICE_RESET SLEEP LP_EN - TEMP_DIS CLKSEL[2:0] */
51#define PWR_DEVICE_RESET BIT(7)
52#define PWR_SLEEP BIT(6)
53#define PWR_LP_EN BIT(5)
54#define PWR_TEMP_DIS BIT(3)
55#define PWR_CLKSEL_MASK 0x07
56#define PWR_CLKSEL_INT_20MHZ 0x01
57#define PWR_CLKSEL_AUTO 0x01 /* typical: auto selects best source */
58
59#define PWR_MGMT_2 0x07 /* - DISABLE_ACCEL DISABLE_GYRO */
60#define PWR_DISABLE_ACCEL BIT(3)
61#define PWR_DISABLE_GYRO BIT(0)
62
63//Interrupt Configs register
64#define INT_PIN_CFG 0x0F /* INT1_ACTL INT1_OPEN INT1_LATCH_INT_EN INT_ANYRD_2CLEAR ACTL_FSYNC FSYNC_INT_MODE_EN BYPASS_EN - */
65#define INT1_ACTL BIT(7) /* active low */
66#define INT1_OPEN BIT(6) /* open-drain */
67#define INT1_LATCH_INT_EN BIT(5) /* latch until status read */
68#define INT_ANYRD_2CLEAR BIT(4)
69#define INT_ACTL_FSYNC BIT(3)
70#define FSYNC_INT_MODE_EN BIT(2)
71#define BYPASS_EN BIT(1) /* I2C bypass to aux devices */
72
73#define INT_ENABLE 0x10 /* REG_WOF_EN - WOM_INT_EN PLL_RDY_EN DMP_INT1_EN I2C_MST_INT_EN */
74#define INT_REG_WOF_EN BIT(7)
75#define INT_WOM_INT_EN BIT(3)
76#define INT_PLL_RDY_EN BIT(2)
77#define INT_DMP_INT1_EN BIT(1)
78#define INT_I2C_MST_INT_EN BIT(0)
79
80#define INT_ENABLE_1 0x11 /* RAW_DATA_0_RDY_EN */
81#define INT_RAW_DATA_0_RDY_EN BIT(0)
82
83#define INT_ENABLE_2 0x12 /* FIFO_OVERFLOW_EN[4:0] */
84#define INT_ENABLE_3 0x13 /* FIFO_WM_EN[4:0] */
85
86#define I2C_MST_STATUS 0x17 /* PASS_THROUGH, *_DONE, *_NACK, LOST_ARB */
87#define MST_PASS_THROUGH BIT(7)
88#define MST_SLV4_DONE BIT(6)
89#define MST_LOST_ARB BIT(5)
90#define MST_SLV4_NACK BIT(4)
91#define MST_SLV3_NACK BIT(3)
92#define MST_SLV2_NACK BIT(2)
93#define MST_SLV1_NACK BIT(1)
94#define MST_SLV0_NACK BIT(0)
95
96#define INT_STATUS 0x19 /* WOM_INT PLL_RDY_INT DMP_INT1 I2C_MST_INT */
97#define STS_WOM_INT BIT(3)
98#define STS_PLL_RDY_INT BIT(2)
99#define STS_DMP_INT1 BIT(1)
100#define STS_I2C_MST_INT BIT(0)
101
102#define INT_STATUS_1 0x1A /* RAW_DATA_0_RDY_INT */
103#define STS_RAW_DATA_0_RDY_INT BIT(0)
104#define INT_STATUS_2 0x1B /* FIFO_OVERFLOW_INT[4:0] */
105#define INT_STATUS_3 0x1C /* FIFO_WM_INT[4:0] */
106
107#define DELAY_TIMEH 0x28
108#define DELAY_TIMEL 0x29
109
110/* - Sensor outputs */
111#define ACCEL_XOUT_H 0x2D
112#define ACCEL_XOUT_L 0x2E
113#define ACCEL_YOUT_H 0x2F
114#define ACCEL_YOUT_L 0x30
115#define ACCEL_ZOUT_H 0x31
116#define ACCEL_ZOUT_L 0x32
117#define GYRO_XOUT_H 0x33
118#define GYRO_XOUT_L 0x34
119#define GYRO_YOUT_H 0x35
120#define GYRO_YOUT_L 0x36
121#define GYRO_ZOUT_H 0x37
122#define GYRO_ZOUT_L 0x38
123#define TEMP_OUT_H 0x39
124#define TEMP_OUT_L 0x3A
125
126/* - External sensor shadow data (aux I2C) */
127#define EXT_SLV_SENS_DATA_00 0x3B
128#define EXT_SLV_SENS_DATA_23 0x52 /* contiguous range 0x3B..0x52 */
129
130#define FIFO_EN_1 0x66 /* SLV3..SLV0 FIFO_EN */
131#define FIFO_EN_2 0x67 /* ACCEL GYRO_Z/Y/X TEMP FIFO_EN */
132#define FIFO_RST 0x68 /* FIFO_RESET[4:0] */
133#define FIFO_MODE 0x69 /* FIFO_MODE[4:0] */
134#define FIFO_COUNTH 0x70
135#define FIFO_COUNTL 0x71
136#define FIFO_R_W 0x72
137// #define DATA_RDY_STATUS 0x74 /* WOF_STATUS RAW_DATA_RDY[3:0] */
138#define FIFO_CFG 0x76
139
140#define REG_BANK_SEL 0x7F /* USER_BANK[1:0] */
141
142/* ========================================================================== */
143/* BANK 1 */
144/* ========================================================================== */
145
146/** - Self-test / accel offsets / timebase */
147#define SELF_TEST_X_GYRO 0x02 /* XG_ST_DATA[7:0] */
148#define SELF_TEST_Y_GYRO 0x03 /* YG_ST_DATA[7:0] */
149#define SELF_TEST_Z_GYRO 0x04 /* ZG_ST_DATA[7:0] */
150#define SELF_TEST_X_ACCEL 0x0E /* XA_ST_DATA[7:0] */
151#define SELF_TEST_Y_ACCEL 0x0F /* YA_ST_DATA[7:0] */
152#define SELF_TEST_Z_ACCEL 0x10 /* ZA_ST_DATA[7:0] */
153
154#define XA_OFFS_H 0x14 /* XA_OFFS[14:7] */
155#define XA_OFFS_L 0x15 /* XA_OFFS[6:0] */
156#define YA_OFFS_H 0x17 /* YA_OFFS[14:7] */
157#define YA_OFFS_L 0x18 /* YA_OFFS[6:0] */
158#define ZA_OFFS_H 0x1A /* ZA_OFFS[14:7] */
159#define ZA_OFFS_L 0x1B /* ZA_OFFS[6:0] */
160
161#define TIMEBASE_CORRECTION_PLL 0x28 /* TBC_PLL[7:0] */
162
163#define BANK1_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
164
165/* ========================================================================== */
166/* BANK 2 */
167/* ========================================================================== */
168
169/** - Gyro/Accel configuration, offsets, FSYNC, temperature filter */
170#define GYRO_SMPLRT_DIV 0x00 /* GYRO_SMPLRT_DIV[7:0] */
171
172#define GYRO_CONFIG_1 0x01 /* GYRO_DLPFCFG[2:0] GYRO_FS_SEL[1:0] GYRO_FCHOICE */
173#define GYRO_FCHOICE BIT(0) /* when 0: DLPF on, when 1: off (per datasheet) */
174#define GYRO_FS_SEL_SHIFT 1
175#define GYRO_FS_SEL_MASK (0x3u << GYRO_FS_SEL_SHIFT)
176#define GYRO_FS_250DPS (0u << GYRO_FS_SEL_SHIFT)
177#define GYRO_FS_500DPS (1u << GYRO_FS_SEL_SHIFT)
178#define GYRO_FS_1000DPS (2u << GYRO_FS_SEL_SHIFT)
179#define GYRO_FS_2000DPS (3u << GYRO_FS_SEL_SHIFT)
180#define GYRO_DLPFCFG_SHIFT 5
181#define GYRO_DLPFCFG_MASK (0x7u << GYRO_DLPFCFG_SHIFT)
182
183#define GYRO_CONFIG_2 0x02 /* XGYRO_CTEN YGYRO_CTEN ZGYRO_CTEN GYRO_AVGCFG[2:0] */
184#define XGYRO_CTEN BIT(5)
185#define YGYRO_CTEN BIT(4)
186#define ZGYRO_CTEN BIT(3)
187#define GYRO_AVGCFG_SHIFT 0
188#define GYRO_AVGCFG_MASK (0x7u << GYRO_AVGCFG_SHIFT)
189
190#define XG_OFFS_USRH 0x03
191#define XG_OFFS_USRL 0x04
192#define YG_OFFS_USRH 0x05
193#define YG_OFFS_USRL 0x06
194#define ZG_OFFS_USRH 0x07
195#define ZG_OFFS_USRL 0x08
196
197#define ODR_ALIGN_EN 0x09 /* ODR_ALIGN_EN */
198#define ODR_ALIGN_EN_BIT BIT(0)
199
200#define ACCEL_SMPLRT_DIV_1 0x10 /* ACCEL_SMPLRT_DIV[11:8] */
201#define ACCEL_SMPLRT_DIV_2 0x11 /* ACCEL_SMPLRT_DIV[7:0] */
202
203#define ACCEL_INTEL_CTRL 0x12 /* ACCEL_INTEL_EN ACCEL_INTEL_MODE_INT */
204#define ACCEL_INTEL_EN BIT(7)
205#define ACCEL_INTEL_MODE_INT BIT(6)
206
207#define ACCEL_WOM_THR 0x13 /* WOM_THRESHOLD[7:0] */
208
209#define ACCEL_CONFIG 0x14 /* ACCEL_DLPFCFG[2:0] ACCEL_FS_SEL[1:0] ACCEL_FCHOICE */
210#define ACCEL_FCHOICE BIT(0)
211#define ACCEL_FS_SEL_SHIFT 1
212#define ACCEL_FS_SEL_MASK (0x3u << ACCEL_FS_SEL_SHIFT)
213#define ACCEL_FS_2G (0u << ACCEL_FS_SEL_SHIFT)
214#define ACCEL_FS_4G (1u << ACCEL_FS_SEL_SHIFT)
215#define ACCEL_FS_8G (2u << ACCEL_FS_SEL_SHIFT)
216#define ACCEL_FS_16G (3u << ACCEL_FS_SEL_SHIFT)
217#define ACCEL_DLPFCFG_SHIFT 5
218#define ACCEL_DLPFCFG_MASK (0x7u << ACCEL_DLPFCFG_SHIFT)
219
220#define ACCEL_CONFIG_2 0x15 /* AX_ST_EN_REG AY_ST_EN_REG AZ_ST_EN_REG DEC3_CFG[1:0] */
221#define AX_ST_EN_REG BIT(7)
222#define AY_ST_EN_REG BIT(6)
223#define AZ_ST_EN_REG BIT(5)
224#define DEC3_CFG_SHIFT 0
225#define DEC3_CFG_MASK (0x3u << DEC3_CFG_SHIFT)
226
227#define FSYNC_CONFIG 0x52 /* DELAY_TIME_EN WOF_DEGLITCH_EN WOF_EDGE_INT EXT_SYNC_SET[3:0] */
228#define DELAY_TIME_EN BIT(7)
229#define WOF_DEGLITCH_EN BIT(6)
230#define WOF_EDGE_INT BIT(5)
231#define EXT_SYNC_SET_MASK 0x0F
232
233#define TEMP_CONFIG 0x53 /* TEMP_DLPFCFG[2:0] */
234#define TEMP_DLPFCFG_SHIFT 5
235#define TEMP_DLPFCFG_MASK (0x7u << TEMP_DLPFCFG_SHIFT)
236
237#define MOD_CTRL_USR 0x54 /* REG_LP_DMP_EN */
238#define REG_LP_DMP_EN BIT(7)
239
240#define BANK2_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
241
242/* ========================================================================== */
243/* BANK 3 */
244/* ========================================================================== */
245
246/** - I2C master (aux) interface and slave windows */
247#define I2C_MST_ODR_CONFIG 0x00 /* I2C_MST_ODR_CONFIG[3:0] */
248#define MST_ODR_CFG_MASK 0x0F
249
250#define I2C_MST_CTRL 0x01 /* MULT_MST_EN - I2C_MST_P_NSR I2C_MST_CLK[3:0] */
251#define MULT_MST_EN BIT(7)
252#define I2C_MST_P_NSR BIT(4)
253#define I2C_MST_CLK_MASK 0x0F
254
255#define I2C_MST_DELAY_CTRL 0x02 /* DELAY_ES_SHADOW + I2C_SLVx_DELAY_EN bits */
256#define DELAY_ES_SHADOW BIT(7)
257#define I2C_SLV4_DELAY_EN BIT(4)
258#define I2C_SLV3_DELAY_EN BIT(3)
259#define I2C_SLV2_DELAY_EN BIT(2)
260#define I2C_SLV1_DELAY_EN BIT(1)
261#define I2C_SLV0_DELAY_EN BIT(0)
262
263#define I2C_SLV0_ADDR 0x03 /* RNW + ID[6:0] */
264#define I2C_SLVx_RNW BIT(7)
265#define I2C_SLV0_REG 0x04
266#define I2C_SLV0_CTRL 0x05 /* EN BYTE_SW REG_DIS GRP LENG[3:0] */
267#define I2C_SLVx_EN BIT(7)
268#define I2C_SLVx_BYTE_SW BIT(6)
269#define I2C_SLVx_REG_DIS BIT(5)
270#define I2C_SLVx_GRP BIT(4)
271#define I2C_SLVx_LENG_MASK 0x0F
272#define I2C_SLV0_DO 0x06
273
274#define I2C_SLV1_ADDR 0x07
275#define I2C_SLV1_REG 0x08
276#define I2C_SLV1_CTRL 0x09
277#define I2C_SLV1_DO 0x0A
278
279#define I2C_SLV2_ADDR 0x0B
280#define I2C_SLV2_REG 0x0C
281#define I2C_SLV2_CTRL 0x0D
282#define I2C_SLV2_DO 0x0E
283
284#define I2C_SLV3_ADDR 0x0F
285#define I2C_SLV3_REG 0x10
286#define I2C_SLV3_CTRL 0x11
287#define I2C_SLV3_DO 0x12
288
289#define I2C_SLV4_ADDR 0x13
290#define I2C_SLV4_REG 0x14
291#define I2C_SLV4_CTRL 0x15 /* EN BYTE_SW REG_DIS DLY[4:0] */
292#define I2C_SLV4_DLY_MASK 0x1F
293#define I2C_SLV4_DO 0x16
294#define I2C_SLV4_DI 0x17
295
296#define BANK3_REG_BANK_SEL 0x7F /* mirror of REG_BANK_SEL */
297
298/* ========================================================================== */
299/* REG_BANK_SEL (all banks) */
300/* ========================================================================== */
301
302#define REG_BANK_SEL_USER_BANK_SHIFT 4
303#define REG_BANK_SEL_USER_BANK_MASK (0x3u << REG_BANK_SEL_USER_BANK_SHIFT)
304#define USER_BANK_0 BANK0
305#define USER_BANK_1 BANK1
306#define USER_BANK_2 BANK2
307#define USER_BANK_3 BANK3
308
309/* AK09916 magnetometer registers (connected internally) */
310#define AK09916_I2C_ADDR 0x0C
311#define AK_WIA2 0x01
312#define AK_ST1 0x10
313#define AK_HXL 0x11
314#define AK_ST2 0x18
315#define AK_CNTL2 0x31
316#define AK_CNTL3 0x32
317#define AK_WIA2_VAL 0x09 /* AK09916C WIA2 expected */
318
319#define INTERNAL_20MHZ 0x00 /* 0: Internal 20 MHz RC */
320#define AUTO_SEL 0x01 /* 1–5: Auto/PLL preferred (use 1 as default) */
321#define CLK_STOP 0x07 /* 7: Stop clock / timing gen reset */
322
323
324/* ------------------ Accelerometer Range ------------------ */
325/** - ±2g / ±4g / ±8g / ±16g (maps to FS_SEL 0..3) */
326#define g2 0
327#define g4 1
328#define g8 2
329#define g16 3
330
331/* ------------- Accelerometer Filter Path (FCHOICE) ------------- */
332/**
333 * Path select for accel:
334 * - ACCEL_FCHOICE_BYPASS : DLPF bypassed (very wide BW, fastest)
335 * - ACCEL_FCHOICE_DLPF : DLPF enabled (use ACCEL_DLPFCFG + SMPLRT_DIV)
336 */
337#define ACCEL_FCHOICE_BYPASS 0
338#define ACCEL_FCHOICE_DLPF 1
339
340/* --------------- Accelerometer DLPF Config (CFG) --------------- */
341/**
342 * ACCEL_DLPFCFG (0..7) — choose cutoff/noise BW set (when DLPF is ON).
343 * Tip: start with ACCEL_DLPFCFG_3 for a good noise/latency tradeoff.
344 */
345#define ACCEL_DLPFCFG_0 0
346#define ACCEL_DLPFCFG_1 1
347#define ACCEL_DLPFCFG_2 2
348#define ACCEL_DLPFCFG_3 3
349#define ACCEL_DLPFCFG_4 4
350#define ACCEL_DLPFCFG_5 5
351#define ACCEL_DLPFCFG_6 6
352#define ACCEL_DLPFCFG_7 7
353
354#define ACCEL_DEC3_AVG_4 0u /* averages 1 or 4 (depends on FCHOICE) */
355#define ACCEL_DEC3_AVG_8 1u
356#define ACCEL_DEC3_AVG_16 2u
357#define ACCEL_DEC3_AVG_32 3u
358
359/* ---- Accel DLPF ODR helper (Hz) : base 1125 Hz, DIV 0..4095 ---- */
360#define ACCEL_SMPLRT_DIV_MIN 0u
361#define ACCEL_SMPLRT_DIV_MAX 4095u
362#define ACCEL_DLPF_BASE_HZ 1125.0f
363#define ACCEL_DLPF_ODR_HZ(div) (ACCEL_DLPF_BASE_HZ / (1.0f + (float)(div)))
364
365/* ---- Accel BYPASS quick reference (FCHOICE=0) ----
366 * 3dB ≈ 1209 Hz, NBW ≈ 1248 Hz, output rate ≈ 4500 Hz
367 * (No divider/ODR control in bypass path.)
368 */
369#define ACCEL_BYPASS_3DB_BW_HZ 1209.0f
370#define ACCEL_BYPASS_NBW_HZ 1248.0f
371#define ACCEL_BYPASS_RATE_HZ 4500.0f
372
373/* (Optional) Accel DLPF nominal bandwidth references (FCHOICE=1)
374 * Keep here for quick docs; exact values depend on datasheet rev.
375 */
376#define ACCEL_DLPF0_3DB_BW_HZ 246.0f
377#define ACCEL_DLPF0_NBW_HZ 265.0f
378#define ACCEL_DLPF1_3DB_BW_HZ 246.0f
379#define ACCEL_DLPF1_NBW_HZ 265.0f
380#define ACCEL_DLPF2_3DB_BW_HZ 111.4f
381#define ACCEL_DLPF2_NBW_HZ 136.0f
382#define ACCEL_DLPF3_3DB_BW_HZ 50.4f
383#define ACCEL_DLPF3_NBW_HZ 68.8f
384#define ACCEL_DLPF4_3DB_BW_HZ 23.9f
385#define ACCEL_DLPF4_NBW_HZ 34.4f
386#define ACCEL_DLPF5_3DB_BW_HZ 11.5f
387#define ACCEL_DLPF5_NBW_HZ 17.0f
388#define ACCEL_DLPF6_3DB_BW_HZ 5.7f
389#define ACCEL_DLPF6_NBW_HZ 8.3f
390#define ACCEL_DLPF7_3DB_BW_HZ 473.0f
391#define ACCEL_DLPF7_NBW_HZ 499.0f
392
393
394/* -------------------- Gyroscope Range -------------------- */
395/** - ±250/±500/±1000/±2000 dps (maps to FS_SEL 0..3) */
396#define dps250 0
397#define dps500 1
398#define dps1000 2
399#define dps2000 3
400
401/* --------------- Gyroscope Filter Path (FCHOICE) --------------- */
402/**
403 * Path select for gyro:
404 * - GYRO_FCHOICE_BYPASS : DLPF bypassed (widest BW, fastest)
405 * - GYRO_FCHOICE_DLPF : DLPF enabled (use GYRO_DLPFCFG + SMPLRT_DIV)
406 */
407#define GYRO_FCHOICE_BYPASS 0
408#define GYRO_FCHOICE_DLPF 1
409
410/* ----------------- Gyroscope DLPF Config (CFG) ----------------- */
411/**
412 * GYRO_DLPFCFG (0..7) — choose cutoff/noise BW set (when DLPF is ON).
413 * Tip: start with GYRO_DLPFCFG_3 or _2 for balanced noise/latency.
414 */
415#define GYRO_DLPFCFG_0 0
416#define GYRO_DLPFCFG_1 1
417#define GYRO_DLPFCFG_2 2
418#define GYRO_DLPFCFG_3 3
419#define GYRO_DLPFCFG_4 4
420#define GYRO_DLPFCFG_5 5
421#define GYRO_DLPFCFG_6 6
422#define GYRO_DLPFCFG_7 7
423
424/* ---- Gyro DLPF ODR helper (Hz) : base 1100 Hz, guard ≥~4.3 Hz ---- */
425#define GYRO_SMPLRT_MIN_HZ 4.3f
426#define GYRO_DLPF_BASE_HZ 1100.0f
427#define GYRO_DLPF_ODR_HZ(rate_request) (rate_request) /* symbolic; your driver computes DIV = round(1100/rate)-1 */
428
429/* (Optional) Gyro BW “buckets” to tag configs in UI/logs (symbolic)
430 * Use these if you want a quick human-readable label for NBW tiers.
431 * Exact Hz depend on datasheet table; map per your implementation.
432 */
433#define GYRO_BW_ULTRA_WIDE 0 /* bypass path */
434#define GYRO_BW_WIDE 1 /* e.g., CFG 0/1 */
435#define GYRO_BW_MEDIUM 2 /* e.g., CFG 2/3 */
436#define GYRO_BW_NARROW 3 /* e.g., CFG 4/5/6/7 */
437
438/* ---------------- Convenience: presets (symbolic) --------------- */
439/** - Friendly ODR presets you can map to dividers */
440#define Hz2 0
441#define Hz6 1
442#define Hz8 2
443#define Hz10 3
444#define Hz15 4
445#define Hz20 5
446#define Hz25 6
447#define Hz30 7
448
449/* ------------------ Power / Fusion Modes ----------------- */
450/**
451 * Generic power or fusion quality modes (BNO-style).
452 * Map to sensor-specific sequences inside your driver.
453 */
454#define LowPower 0
455#define Regular 1
456#define EnhancedRegular 2
457#define HighAccuracy 3
458
459#endif /* ICM20948_REGS_H */