| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| xlr8_spi_2_inst|u_rst_gen |
11 |
0 |
7 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst|u_sckd |
22 |
0 |
11 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst|u_core|u_sck_drv_div2_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst|u_core|u_sck_div2_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst|u_core|u_ss_b_rsnc |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst|u_core |
41 |
3 |
12 |
3 |
35 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_2_inst |
37 |
5 |
0 |
5 |
11 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_rst_gen |
11 |
0 |
7 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_sckd |
22 |
0 |
11 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_core|u_sck_drv_div2_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_core|u_sck_div2_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_core|u_ss_b_rsnc |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst|u_core |
41 |
3 |
12 |
3 |
35 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| xlr8_spi_1_inst |
37 |
5 |
0 |
5 |
11 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| gpio_inst |
30 |
1 |
11 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| uc_top_wrp_vlog_inst |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|mux5 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|mux4 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|decode3 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated|decode2 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst|altsyncram_component|auto_generated |
63 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst|ram16k.ram2p16384x16_inst |
63 |
17 |
0 |
17 |
32 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| p_mem_inst |
52 |
0 |
6 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| d_mem_inst|altsyncram_inst|auto_generated |
22 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| d_mem_inst |
27 |
0 |
5 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| iomux328_inst |
184 |
8 |
6 |
8 |
59 |
8 |
8 |
8 |
22 |
0 |
0 |
0 |
0 |
| xb_pinmux_inst |
82 |
39 |
2 |
39 |
80 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| clocks_inst|int_osc_inst|int_osc_0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| clocks_inst|int_osc_inst |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| clocks_inst|pll_inst|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| clocks_inst|pll_inst |
1 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| clocks_inst |
29 |
1 |
15 |
1 |
18 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |